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CS4223-KS 参数 Datasheet PDF下载

CS4223-KS图片预览
型号: CS4223-KS
PDF下载: 下载PDF文件 查看货源
内容描述: 24位105 dB音频编解码器,带有音量控制 [24-Bit 105 dB Audio Codec with Volume Control]
分类和应用: 解码器编解码器
文件页数/大小: 32 页 / 751 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS4223 CS4224
SWITCHING CHARACTERISTICS
(T
A
= 25° C; VA, VD = 4.75 V - 5.25 V; outputs loaded with
30 pF)
Parameter
Audio ADC’s and DAC’s Sample Rate
XTI Frequency
XTI Pulse Width High
XTI = 256, 384, or 512 Fs
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
(Note 10)
DSCK = 0
DSCK = 0
DSCK = 0
t
dpd
t
lrpd
t
ds
t
dh
t
sckw
t
sckh
t
sckl
DSCK = 0
DSCK = 0
t
lrckd
t
lrcks
Symbol
Fs
Min
4
1.024
13
21
31
13
21
31
-
10
-
-
25
25
1
---------------------
-
(128) Fs
Typ
-
-
-
-
-
-
-
-
500
-
-
-
-
-
-
-
-
-
-
Max
50
26
-
-
-
-
-
-
-
-
1
--------------------- + 20
-
(384) Fs
Unit
kHz
MHz
ns
ns
ns
ns
ns
ns
psRMS
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
XTI Pulse Width Low
XTI Jitter Tolerance
RST Low Time
SCLK falling edge to SDOUT output valid
LRCK edge to MSB valid
SDIN setup time before SCLK rising edge
SDIN hold time after SCLK rising edge
SCLK Period
SCLK High Time
SCLK Low Time
SCLK rising to LRCK edge
LRCK edge to SCLK rising
45
-
-
-
-
-
-
-
40
40
35
40
Notes: 10. After powering up the CS4223/4, PDN should be held low for 10 ms to allow the power supply to settle.
LRCK
t lrckd
t lrcks
t sckh
t sckl
SCLK*
t sckw
SDIN
t lrpd
t ds
t dh
t dpd
SDOUT
MSB
MSB-1
*SCLK shown for DSCK = 0, SCLK inverted for DSCK = 1.
Figure 1. Serial Audio Port Data I/O Timing
DS290PP3
7