CS4202
AC ’97 SERIAL PORT TIMING Standard test conditions unless otherwise noted: T
= 25° C,
ambient
AVdd = 5.0 V, DVdd = 3.3 V; C = 55 pF load.
L
Parameter
RESET Timing
Symbol
Min
Typ
Max
Unit
RESET# active low pulse width
RESET# inactive to BIT_CLK start-up delay
T
1.0
-
-
µs
rst_low
(XTL mode)
(OSC mode)
(PLL mode)
T
-
-
-
4.0
4.0
2.5
-
-
-
µs
µs
ms
rst2clk
1st SYNC active to CODEC READY ‘set’
Vdd stable to RESET# inactive
Clocks
T
-
62.5
-
-
-
µs
µs
sync2crd
T
100
vdd2rst#
BIT_CLK frequency
F
-
-
12.288
81.4
-
-
MHz
ns
clk
BIT_CLK period
T
-
750
45
45
-
clk_period
BIT_CLK output jitter (depends on XTL_IN source)
BIT_CLK high pulse width
-
ps
T
36
36
-
40.7
40.7
48
ns
clk_high
BIT_CLK low pulse width
T
ns
clk_low
SYNC frequency
F
kHz
sync
SYNC period
T
-
20.8
1.3
-
µs
µs
sync_period
SYNC high pulse width
T
-
-
sync_high
SYNC low pulse width
T
-
19.5
-
µs
sync_low
Data Setup and Hold
Output propagation delay from rising edge of BIT_CLK
Input setup time from falling edge of BIT_CLK
Input hold time from falling edge of BIT_CLK
Input signal rise time
T
8
10
0
10
-
12
-
ns
ns
ns
ns
ns
ns
ns
co
T
isetup
T
-
-
ihold
T
2
-
6
6
6
6
irise
Input signal fall time
T
2
-
ifall
Output signal rise time
(Note 4)
(Note 4)
T
2
4
4
orise
Output signal fall time
T
2
ofall
Misc. Timing Parameters
End of Slot 2 to BIT_CLK, SDATA_IN low (PR4)
SYNC pulse width (PR4) Warm Reset
SYNC inactive (PR4) to BIT_CLK start-up delay
T
-
1.0
162.8
15
0.285
1.0
µs
µs
ns
ns
ns
s2_pdown
T
-
-
-
sync_pr4
T
285
sync2clk
Setup to trailing edge of RESET# (ATE test mode) (Note 4)
T
-
-
-
setup2rst
Rising edge of RESET# to Hi-Z delay
(Note 4)
T
-
25
off
DS549PP1
9
CIRRUS [ CIRRUS LOGIC ]
