CS2100-OTP
Fractional-N Clock Multiplier
Features
Clock Multiplier / Jitter Reduction
General Description
The CS2100-OTP is an extremely versatile system
clocking device that utilizes a programmable phase lock
loop. The CS2100-OTP is based on a hybrid analog-
digital PLL architecture comprised of a unique combina-
tion of a Delta-Sigma Fractional-N Frequency
Synthesizer and a Digital PLL. This architecture allows
for generation of a low-jitter clock relative to an external
noisy synchronization clock with frequencies as low as
50 Hz. The CS2100-OTP has many configuration op-
tions which are set once prior to runtime. At runtime
there are three hardware configuration pins available for
mode and feature selection.
The CS2100-OTP is available in a 10-pin MSOP pack-
age in Commercial (-10°C to +70°C) grade. Customer
development kits are also available for custom device
prototyping, small production programming, and device
evaluation. Please see
for complete details.
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Generates a Low Jitter 6 - 75 MHz Clock
from a Jittery or Intermittent 50 Hz to 30
MHz Clock Source
Maximum Error Less Than 1 PPM in High-
Resolution Mode
Configurable Hardware Control Pins
Configurable Auxiliary Output
External Oscillator or Clock Source
Supports Inexpensive Local Crystal
No External Analog Loop-filter
Components
Highly Accurate PLL Multiplication Factor
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One-Time Programmability
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Flexible Sourcing of Reference Clock
Minimal Board Space Required
3.3 V
Timing Reference
Frequency Reference
PLL Output
Lock Indicator
Hardware
Control
Hardware Configuration
Auxiliary
Output
8 MHz to 75 MHz
Low-Jitter Timing
Reference
Fractional-N
Frequency Synthesizer
N
6 to 75 MHz
PLL Output
50 Hz to 30 MHz
Frequency
Reference
Output to Input
Clock Ratio
Digital PLL &
Fractional N Logic
Copyright
Cirrus Logic, Inc. 2009
(All Rights Reserved)
AUG '09
DS841F1
CIRRUS [ CIRRUS LOGIC ]
