CS2100-CP
CONTROL PORT SWITCHING CHARACTERISTICS - SPI FORMAT
Inputs: Logic 0 = GND; Logic 1 = VD; C
L
= 20 pF.
Parameter
CCLK Clock Frequency
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Delay from Supply Voltage Stable to Control Port Ready
(Note
13)
(Note
14)
(Note
14)
(Note
12)
Symbol
f
ccllk
t
spi
t
csh
t
css
t
scl
t
sch
t
dsu
t
dh
t
r2
t
f2
t
dpor
Min
-
500
1.0
20
66
66
40
15
-
-
100
Max
6
-
-
-
-
-
-
-
100
100
-
Unit
MHz
ns
µs
ns
ns
ns
ns
ns
ns
ns
µs
Notes:
12.
t
spi
is only needed before first falling edge of CS after power is applied.
t
spi
= 0 at all other times.
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For f
cclk
< 1 MHz.
VD
t
dpor
CS
t
spi
CCLK
t
r2
CDIN
t
css
t
scl
t
sch
t
csh
t
f2
t
dsu
t
dh
Figure 3. Control Port Timing - SPI Format (Write Only)
DS840PP1
9
CIRRUS [ CIRRUS LOGIC ]
