CS2100-CP
5.1.3
External Reference Clock (REF_CLK)
For operation with an externally generated REF_CLK signal, XTI/REF_CLK should be connected to the
reference clock source and XTO should be left unconnected or pulled low through a 47 kΩ resistor to
GND.
5.2
Frequency Reference Clock Input, CLK_IN
The frequency reference clock input (CLK_IN) is used by the Digital PLL and Fractional-N Logic block to
dynamically generate a fractional-N value for the Frequency Synthesizer (see “Hybrid Analog-Digital PLL”
on page 11). The Digital PLL first compares the CLK_IN frequency to the PLL output. The Fractional-N logic
block then translates the desired ratio based off of CLK_IN to one based off of the internal timing reference
clock (SysClk). This allows the low-jitter timing reference clock to be used as the clock which the Frequency
Synthesizer multiplies while maintaining synchronicity with the frequency reference clock through the Digital
PLL. The allowable frequency range for CLK_IN is found in the “AC Electrical Characteristics” on page 7.
5.2.1
CLK_IN Frequency Detector
The CLK_IN frequency range detector determines and indicates the ratio between the frequency of the
internal SysClk and the CLK_IN input signal.
The result of the ratio measurement is available in the read-only FsDet[1:0] bits and is also used by the
device to determine the Auto R-Mod value.
f
/ f
Ratio
FsDetect[1:0]
SysClk CLK_IN
00
01
10
11
> 224
96 - 224
< 96
Reserved
Table 1. PLL Input Clock Range Indicator
is known, FsDet[1:0] can then be interpreted as a range for f
Because f
. This feature is par-
CLK_IN
SysClk
ticularly useful when used in conjunction with the Auto R-Mod feature (see section 5.3.3 on page 17).
Referenced Control
Register Location
FsDet[1:0]..............................“PLL Input Sample Rate Indicator (FsDet[1:0]) - Read Only” section on page 25
5.2.2
CLK_IN Skipping Mode
CLK_IN skipping mode allows the PLL to maintain lock even when the CLK_IN signal has missing pulses
for up to 20 ms (t ) at a time (see “AC Electrical Characteristics” on page 7 for specifications). CLK_IN
CS
skipping mode can only be used when the CLK_IN frequency is below 80 kHz. The ClkSkipEn bit enables
this function.
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Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 2 SysClk cycles (466 ms
to 1048 ms) after CLK_IN is removed (see Figure 8). This is true as long as CLK_IN does not glitch or
have an effective change in period as the clock source is removed, otherwise the PLL will interpret this as
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a change in frequency causing clock skipping and the 2 SysClk cycle time-out to be bypassed and the
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PLL to immediately unlock. If the prior conditions are met while CLK_IN is removed and 2 SysClk cycles
pass, the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl bit; See “PLL Clock
Output” on page 20. If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified
DS840PP1
13
CIRRUS [ CIRRUS LOGIC ]
