CS2000-OTP
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 4
2. TYPICAL CONNECTION DIAGRAM ..................................................................................................... 5
3. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6
RECOMMENDED OPERATING CONDITIONS .................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6
DC ELECTRICAL CHARACTERISTICS ................................................................................................ 6
AC ELECTRICAL CHARACTERISTICS ................................................................................................ 7
4. ARCHITECTURE OVERVIEW ............................................................................................................... 8
4.1 Delta-Sigma Fractional-N Frequency Synthesizer ........................................................................... 8
4.2 Hybrid Analog-Digital Phase Locked Loop ...................................................................................... 8
4.2.1 Fractional-N Source Selection for the Frequency Synthesizer ................................................ 9
5. APPLICATIONS ................................................................................................................................... 10
5.1 One Time Programmability ............................................................................................................ 10
5.2 Timing Reference Clock Input ........................................................................................................ 10
5.2.1 Internal Timing Reference Clock Divider ............................................................................... 10
5.2.2 Crystal Connections (XTI and XTO) ...................................................................................... 11
5.2.3 External Reference Clock (REF_CLK) .................................................................................. 11
5.3 Frequency Reference Clock Input, CLK_IN ................................................................................... 11
5.3.1 CLK_IN Skipping Mode ......................................................................................................... 11
5.3.2 Adjusting the Minimum Loop Bandwidth for CLK_IN ............................................................ 13
5.4 Output to Input Frequency Ratio Configuration ............................................................................. 14
5.4.1 User Defined Ratio (RUD), Frequency Synthesizer Mode .................................................... 14
5.4.2 User Defined Ratio (RUD), Hybrid PLL Mode ....................................................................... 14
5.4.3 Manual Ratio Modifier (R-Mod) ............................................................................................. 15
5.4.4 Automatic Ratio Modifier (Auto R-Mod) - Hybrid PLL Mode Only ......................................... 15
5.4.5 Effective Ratio (REFF) .......................................................................................................... 16
5.4.6 Fractional-N Source Selection ............................................................................................... 16
5.4.6.1 Manual Fractional-N Source Selection for the Frequency Synthesizer ..................... 17
5.4.6.2 Automatic Fractional-N Source Selection for the Frequency Synthesizer ................. 17
5.4.7 Ratio Configuration Summary ............................................................................................... 18
5.5 PLL Clock Output ........................................................................................................................... 19
5.6 Auxiliary Output .............................................................................................................................. 19
5.7 Mode Pin Functionality ................................................................................................................... 20
5.7.1 M1 and M0 Mode Pin Functionality ....................................................................................... 20
5.7.2 M2 Mode Pin Functionality .................................................................................................... 20
5.7.2.1 M2 Configured as Output Disable .............................................................................. 20
5.7.2.2 M2 Configured as R-Mod Enable .............................................................................. 20
5.7.2.3 M2 Configured as Auto Fractional-N Source Selection Disable ................................ 21
5.7.2.4 M2 Configured as Auto R-Mod Enable ...................................................................... 21
5.7.2.5 M2 Configured as Fractional-N Source Select .......................................................... 21
5.7.2.6 M2 Configured as AuxOutSrc Override ..................................................................... 21
5.8 Clock Output Stability Considerations ............................................................................................ 21
5.8.1 Output Switching ................................................................................................................... 21
5.8.2 PLL Unlock Conditions .......................................................................................................... 22
6. PARAMETER DESCRIPTIONS ........................................................................................................... 23
6.1 Modal Configuration Sets ............................................................................................................... 23
6.1.1 R-Mod Selection (RModSel[1:0]) ........................................................................................... 23
6.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0]) ............................................................. 24
6.1.3 Auto R-Modifier Enable (AutoRMod) ..................................................................................... 24
6.1.4 Lock Clock Ratio (LockClk[1:0]) ............................................................................................ 24
6.1.5 Fractional-N Source for Frequency Synthesizer (FracNSrc) ................................................. 24
6.2 Ratio 0 - 3 ...................................................................................................................................... 24
DS758PP1
2
CIRRUS [ CIRRUS LOGIC ]
