CS2000-CP
PLL PERFORMANCE PLOTS
Test Conditions (unless otherwise specified): VD = 3.3 V; T
A
= 25 °C (Commercial Grade); C
L
= 15 pF;
f
CLK_OUT
= 12.288 MHz; f
CLK_IN
= 12.288 MHz; Sample size = 10,000 points; Base Band Jitter (100 Hz to 40 kHz);
AuxOutSrc[1:0]
= 11.
10,000
1 Hz Bandwidth
128 Hz Bandwidth
10
1 Hz Bandwidth
128 Hz Bandwidth
0
1,000
Max Input Jitter Level (usec)
-10
100
Jitter Transfer (dB)
1
10
100
1,000
10,000
-20
10
-30
-40
1
-50
0.1
-60
1
10
100
1000
10000
Input Jitter Frequency (Hz)
Input Jitter Frequency (Hz)
Figure 2. CLK_IN Sinusoidal Jitter Tolerance
Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz).
Figure 3. CLK_IN Sinusoidal Jitter Transfer
Samples size = 2.5M points; Base Band Jitter (10Hz to 40kHz).
1000
1 Hz Bandwidth
128 Hz Bandwidth
100
Output Jitter Level (nsec)
Unlock
10
1
Unlock
0.1
0.01
0.01
0.1
1
10
100
1000
Input Jitter Level (nsec)
Figure 4. CLK_IN Random Jitter Rejection and Tolerance
DS761F1
9
CIRRUS [ CIRRUS LOGIC ]
