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CS2000CP-CZZ 参数 Datasheet PDF下载

CS2000CP-CZZ图片预览
型号: CS2000CP-CZZ
PDF下载: 下载PDF文件 查看货源
内容描述: 小数N分频时钟合成器与时钟乘法器 [Fractional-N Clock Synthesizer & Clock Multiplier]
分类和应用: 时钟
文件页数/大小: 36 页 / 292 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS2000-CP  
9. CALCULATING THE USER DEFINED RATIO  
Note: The software for use with the evaluation kit has built in tools to aid in calculating and converting the User  
Defined Ratio. This section is for those who are not interested in the software or who are developing their  
systems without the aid of the evaluation kit.  
Most calculators do not interpret the fixed point binary representation which the CS2000 uses to define the output  
to input clock ratio (see Section 5.3.1 on page 19); However, with a simple conversion we can use these tools to  
generate a binary or hex value which can be written to the Ratio registers.  
0-3  
9.1  
High Resolution 12.20 Format  
To calculate the User Defined Ratio (R ) to store in the register(s), divide the desired output clock frequen-  
UD  
20  
cy by the given input clock (CLK_IN or RefClk). Then multiply the desired ratio by the scaling factor of 2  
to get the scaled decimal representation; then use the decimal to binary/hex conversion function on a cal-  
culator and write to the register. A few examples have been provided in Table 2.  
Scaled Decimal  
Representation =  
(output clock/input clock) 2  
1288490  
Hex Representation of  
Desired Output to Input Clock Ratio  
(output clock/input clock)  
20  
Binary R  
UD  
12.288 MHz/10 MHz=1.2288  
11.2896 MHz/44.1 kHz=256  
00 13 A9 2A  
10 00 00 00  
268435456  
Table 2. Example 12.20 R-Values  
9.2  
High Multiplication 20.12 Format  
To calculate the User Defined Ratio (R ) to store in the register(s), divide the desired output clock frequen-  
UD  
12  
cy by the given input clock (CLK_IN). Then multiply the desired ratio by the scaling factor of 2 to get the  
scaled decimal representation; then use the decimal to binary/hex conversion function on a calculator and  
write to the register. A few examples have been provided in Table 3.  
Scaled Decimal  
Representation =  
(output clock/input clock) 2  
838860800  
Hex Representation of  
Desired Output to Input Clock Ratio  
(output clock/input clock)  
12  
Binary R  
UD  
12.288 MHz/60 Hz=204,800  
32 00 00 00  
2D F5 E2 08  
11.2896 MHz/59.97 Hz =188254.127...  
771088904  
Table 3. Example 20.12 R-Values  
34  
DS761F1