CS2000-CP
23
Regardless of the setting of the ClkSkipEn bit the PLL output will continue for 2 SysClk cycles (466 ms
to 1048 ms) after CLK_IN is removed (see Figure 13). This is true as long as CLK_IN does not glitch or
have an effective change in period as the clock source is removed, otherwise the PLL will interpret this as
23
a change in frequency causing clock skipping and the 2 SysClk cycle time-out to be bypassed and the
23
PLL to immediately unlock. If the prior conditions are met while CLK_IN is removed and 2 SysClk cycles
pass, the PLL will unlock and the PLL_OUT state will be determined by the ClkOutUnl bit; See “PLL Clock
Output” on page 23. If CLK_IN is re-applied after such time, the PLL will remain unlocked for the specified
time listed in the “AC Electrical Characteristics” on page 8 after which lock will be acquired and the PLL
output will resume.
23
23
2
SysClk cycles
2
SysClk cycles
Lock Time
Lock Time
CLK_IN
PLL_OUT
UNLOCK
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0 or 1
ClkOutUnl=0
ClkSkipEn=0 or 1
ClkOutUnl=1
= invalid clocks
23
Figure 13. CLK_IN removed for > 2 SysClk cycles
23
If it is expected that CLK_IN will be removed and then reapplied within 2 SysClk cycles but later than
t
, the ClkSkipEn bit should be disabled. If it is not disabled, the device will behave as shown in
CS
Figure 14; note that the lower figure shows that the PLL output frequency may change and be incorrect
without an indication of an unlock condition.
23
23
2
SysClk cycles
2
SysClk cycles
tCS
tCS
Lock Time
Lock Time
CLK_IN
PLL_OUT
UNLOCK
CLK_IN
PLL_OUT
UNLOCK
ClkSkipEn=0 or 1
ClkOutUnl=0
ClkSkipEn=0 or 1
ClkOutUnl=1
= invalid clocks
23
2
SysClk cycles
tCS
Lock Time
CLK_IN
ClkSkipEn= 1
ClkOutUnl=1
PLL_OUT
UNLOCK
= invalid clocks
23
Figure 14. CLK_IN removed for < 2 SysClk cycles but > t
CS
16
DS761F1
CIRRUS [ CIRRUS LOGIC ]
