CS2000-CP
5. APPLICATIONS
5.1
Timing Reference Clock Input
The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an
external crystal in conjunction with the internal oscillator. In order to maintain a stable and low-jitter PLL out-
put the timing reference clock must also be stable and low-jitter; the quality of the timing reference clock
directly affects the performance of the PLL and hence the quality of the PLL output.
5.1.1
Internal Timing Reference Clock Divider
The Internal Timing Reference Clock (SysClk) has a smaller maximum frequency than what is allowed on
the XTI/REF_CLK pin. The CS2000 supports the wider external frequency range by offering an internal
divider for RefClk. The RefClkDiv[1:0] bits should be set such that SysClk, the divided RefClk, then falls
within the valid range as indicated in “AC Electrical Characteristics” on page 8.
Timing Reference
Internal Timing
Clock Divider
Fractional-N
Frequency
Synthesizer
Reference Clock
Timing Reference Clock
÷1
÷2
÷4
XTI/REF_CLK
PLL Output
50 MHz (XTI)
8 MHz < RefClk <
8 MHz < SysClk < 14 MHz
58 MHz (REF_CLK)
N
RefClkDiv[1:0]
Figure 10. Internal Timing Reference Clock Divider
It should be noted that the maximum allowable input frequency of the XTI/REF_CLK pin is dependent
upon its configuration as either a crystal connection or external clock input. See the “AC Electrical Char-
acteristics” on page 8 for more details.
For the lowest possible output jitter, attention should be paid to the absolute frequency of the Timing Ref-
erence Clock relative to the PLL Output frequency (CLK_OUT). To minimize output jitter, the Timing Ref-
erence Clock frequency should be chosen such that f
is at least +/-15 kHz from f
*N/32
RefClk
CLK_OUT
where N is an integer. Figure 11 shows the effect of varying the RefClk frequency around f
*N/32.
CLK_OUT
It should be noted that there will be a jitter null at the zero point when N = 32 (not shown in Figure 11). An
example of how to determine the range of RefClk frequencies around 12 MHz to be used in order to
achieve the lowest jitter PLL output at a frequency of 12.288 MHz is as follows:
fL ≤ fRefClk ≤ fH where:
CLK__OUT Jitter
180
*32/N
f
CLK__OUT
160
140
120
100
80
31
32
fL = fCLK_OUT × ----- + 15kHz
= 12.288MHz × 0.96875 + 15kHz
= 11.919MHz
-15 kHz
+15 kHz
and
60
32
32
fH = fCLK_OUT × ----- – 15kHz
40
= 12.288MHz × 1 + 15kHz
20
-80
-60
-40
-20
0
20
40
60
80
= 12.273MHz
Normalized REF__CLK Frequency (kHz)
Figure 11. REF_CLK Frequency vs a Fixed CLK_OUT
Referenced Control
Register Location
RefClkDiv[1:0] .......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 32
14
DS761F1
CIRRUS [ CIRRUS LOGIC ]
