CS2000-CP
AC ELECTRICAL CHARACTERISTICS
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T
A
= -10°C to +70°C (Commercial Grade);
C
L
= 15 pF.
Parameters
Crystal Frequency
Reference Clock Input Frequency
Reference Clock Input Duty Cycle
Internal System Clock Frequency
Clock Input Frequency (Auto R-Mod Disabled)
Clock Input Frequency (Auto R-mod Enabled)
Symbol
f
XTAL
f
REF_CLK
D
REF_CLK
f
SYS_CLK
f
CLK_IN
f
CLK_IN
Conditions
Fundamental Mode
Min
8
8
45
8
50 Hz
Typ
-
-
-
-
-
-
-
-
-
-
-
-
50
1.7
1.7
70
50
175
100
1
1
-
-
Max
50
75
55
18.75
30
59
138
256
-
-
-
80
75
52
3.0
3.0
150
-
-
200
3
2
±0.5
±112
Units
MHz
MHz
%
MHz
MHz
kHz
kHz
kHz
UI
ns
ms
kHz
MHz
%
ns
ns
ps rms
ps rms
ps rms
UI
ms
ms
ppm
ppm
Auto R Modifier = 1
Auto R Modifier = 0.5
Auto R Modifier = 0.25
f
CLK_IN
< f
SYS_CLK
/96
f
CLK_IN
> f
SYS_CLK
/96
(Notes
4, 5)
(Note
5)
Measured at VD/2
20% to 80% of VD
80% to 20% of VD
(Note
6)
(Notes
6, 7)
(Notes
6, 8)
4
72
168
2
10
20
50 Hz
6
48
-
-
-
-
-
-
-
-
0
0
Clock Input Pulse Width (Note
3)
Clock Skipping Timeout
Clock Skipping Input Frequency
PLL Clock Output Frequency
PLL Clock Output Duty Cycle
Clock Output Rise Time
Clock Output Fall Time
Period Jitter
Base Band Jitter (100 Hz to 40 kHz)
Wide Band JItter (100 Hz Corner)
PLL Lock Time - CLK_IN (Note
9)
PLL Lock Time - REF_CLK
Output Frequency Synthesis Resolution (Note
10)
pw
CLK_IN
t
CS
f
CLK_SKIP
f
CLK_OUT
t
OD
t
OR
t
OF
t
JIT
t
LC
t
LR
f
err
f
CLK_IN
< 200 kHz
f
CLK_IN
> 200 kHz
f
REF_CLK
= 8 to 75 MHz
High Resolution
High Multiplication
Notes:
3. 1 UI (unit interval) corresponds to t
SYS_CLK
or 1/f
SYS_CLK
.
4. t
CS
represents the time from the removal of CLK_IN by which CLK_IN must be re-applied to ensure that
PLL_OUT continues while the PLL re-acquires lock. This timeout is based on the internal VCO frequen-
cy, with the minimum timeout occurring at the maximum VCO frequency. Lower VCO frequencies will
result in larger values of t
CS
.
5. Only valid in clock skipping mode; See
“CLK_IN Skipping Mode” on page 14
for more information.
6.
f
CLK_OUT
= 24.576 MHz; Sample size = 10,000 points; AuxOutSrc[1:0] = 11.
7. In accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error taken with 3rd
order 100 Hz to 40 kHz bandpass filter.
8. In accordance with AES-12id-2006 section 3.4.1. Measurements are Time Interval Error taken with 3rd
order 100 Hz Highpass filter.
9. 1 UI (unit interval) corresponds to t
CLK_IN
or 1/f
CLK_IN
.
10. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the
reference clock.
8
DS761PP1
CIRRUS [ CIRRUS LOGIC ]
