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CS2000-CP-CZZ 参数 Datasheet PDF下载

CS2000-CP-CZZ图片预览
型号: CS2000-CP-CZZ
PDF下载: 下载PDF文件 查看货源
内容描述: 小数N分频时钟合成器与时钟乘法器 [Fractional-N Clock Synthesizer & Clock Multiplier]
分类和应用: 时钟
文件页数/大小: 36 页 / 425 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS2000-CP  
3. CHARACTERISTICS AND SPECIFICATIONS  
RECOMMENDED OPERATING CONDITIONS  
GND = 0 V; all voltages with respect to ground. (Note 1)  
Parameters  
Symbol  
Min  
Typ  
Max  
Units  
DC Power Supply  
Ambient Operating Temperature (Power Applied)  
VD  
3.1  
3.3  
3.5  
V
Commercial Grade  
TAC  
-10  
-
+70  
°C  
Notes: 1. Device functional operation is guaranteed within these limits. Functionality is not guaranteed or implied  
outside of these limits. Operation outside of these limits may adversely affect device reliability.  
ABSOLUTE MAXIMUM RATINGS  
GND = 0 V; all voltages with respect to ground.  
Parameters  
Symbol  
VD  
Min  
-0.3  
-
Max  
6.0  
Units  
V
DC Power Supply  
Input Current  
IIN  
±10  
mA  
V
Digital Input Voltage (Note 1)  
VIN  
-0.3  
-55  
-65  
VD + 0.4  
125  
Ambient Operating Temperature (Power Applied)  
Storage Temperature  
TA  
°C  
Tstg  
150  
°C  
WARNING: Operation at or beyond these limits may result in permanent damage to the device.  
Notes: 1. The maximum over/under voltage is limited by the input current except on the power supply pin.  
DC ELECTRICAL CHARACTERISTICS  
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T = -10°C to +70°C (Commercial Grade).  
A
Parameters  
Power Supply Current - Unloaded  
Symbol  
ID  
Min  
Typ  
Max  
18  
60  
±10  
-
Units  
mA  
mW  
µA  
(Note 2)  
(Note 2)  
-
12  
40  
-
Power Dissipation - Unloaded  
Input Leakage Current  
PD  
-
IIN  
-
-
Input Capacitance  
IC  
8
-
pF  
High-Level Input Voltage  
Low-Level Input Voltage  
VIH  
VIL  
70%  
-
-
VD  
-
30%  
-
VD  
High-Level Output Voltage (IOH = -1.2 mA)  
VOH  
80%  
-
VD  
Low-Level Output Voltage (IOH = 1.2 mA)  
VOL  
-
-
20%  
VD  
Notes: 2. To calculate the additional current consumption due to loading (per output pin), multiply clock output  
frequency by load capacitance and power supply voltage.  
For example, fCLK_OUT (49.152 MHz) * C (15 pF) * VD (3.3 V) = 2.4 mA of additional current due to  
L
these loading conditions on CLK_OUT.  
DS761PP1  
7