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CS2000-CP_09 参数 Datasheet PDF下载

CS2000-CP_09图片预览
型号: CS2000-CP_09
PDF下载: 下载PDF文件 查看货源
内容描述: 小数N分频时钟合成器与时钟乘法器 [Fractional-N Clock Synthesizer & Clock Multiplier]
分类和应用: 时钟
文件页数/大小: 36 页 / 292 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS2000-CP  
5.4  
PLL Clock Output  
The PLL clock output pin (CLK_OUT) provides a buffered version of the output of the frequency synthesizer.  
The driver can be set to high-impedance with the ClkOutDis bit.  
The output from the PLL automatically drives a static low condition while the PLL is un-locked (when the  
clock may be unreliable). This feature can be disabled by setting the ClkOutUnl bit, however the state  
CLK_OUT may then be unreliable during an unlock condition.  
ClkOutUnl  
PLL Locked/Unlocked  
0
0
ClkOutDis  
0
2:1 Mux  
1
PLL Clock Output  
PLLClkOut  
PLL Clock Output Pin  
(CLK_OUT)  
2:1 Mux  
PLL Output  
1
Figure 19. PLL Clock Output Options  
Referenced Control  
Register Location  
ClkOutUnl..............................“Enable PLL Clock Output on Unlock (ClkOutUnl)” on page 32  
ClkOutDis..............................“PLL Clock Output Disable (ClkOutDis)” on page 29  
5.5  
Auxiliary Output  
The auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 20, to one of four signals: refer-  
ence clock (RefClk), input clock (CLK_IN), additional PLL clock output (CLK_OUT), or a PLL lock indicator  
(Lock). The mux is controlled via the AuxOutSrc[1:0] bits. If AUX_OUT is set to Lock, the AuxLockCfg bit is  
then used to control the output driver type and polarity of the LOCK signal (see section 8.7.2 on page 32).  
If AUX_OUT is set to CLK_OUT the phase of the PLL Clock Output signal on AUX_OUT may differ from the  
CLK_OUT pin. The driver for the pin can be set to high-impedance using the AuxOutDis bit.  
AuxOutSrc[1:0]  
Timing Reference Clock  
(RefClk)  
AuxOutDis  
Frequency Reference Clock  
(CLK_IN)  
Auxiliary Output Pin  
(AUX_OUT)  
4:1 Mux  
PLL Clock Output  
(PLLClkOut)  
AuxLockCfg  
PLL Lock/Unlock Indication  
(Lock)  
Figure 20. Auxiliary Output Selection  
Referenced Control  
Register Location  
AuxOutSrc[1:0]......................“Auxiliary Output Source Selection (AuxOutSrc[1:0])” on page 29  
AuxOutDis.............................“Auxiliary Output Disable (AuxOutDis)” on page 28  
AuxLockCfg...........................“AUX PLL Lock Output Configuration (AuxLockCfg)” section on page 32  
DS761F1  
23