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CS2000-CP-DZZR 参数 Datasheet PDF下载

CS2000-CP-DZZR图片预览
型号: CS2000-CP-DZZR
PDF下载: 下载PDF文件 查看货源
内容描述: [PHASE LOCKED LOOP, 75MHz, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10]
分类和应用: 光电二极管
文件页数/大小: 32 页 / 594 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS2000-CP  
AC ELECTRICAL CHARACTERISTICS  
Test Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; T = -10°C to +70°C (Commercial Grade);  
A
T = -40°C to +85°C (Automotive Grade); C = 15 pF.  
A
L
Parameters  
Symbol  
fXTAL  
Conditions  
Min  
Typ  
Max Units  
Crystal Frequency  
Fundamental Mode  
8
-
-
50  
75  
55  
30  
-
MHz  
MHz  
%
Reference Clock Input Frequency  
Reference Clock Input Duty Cycle  
Clock Input Frequency  
fREF_CLK  
DREF_CLK  
fCLK_IN  
pwCLK_IN  
fCLK_OUT  
tOD  
8
45  
-
50 Hz  
-
MHz  
ns  
Clock Input Pulse Width  
10  
6
-
PLL Clock Output Frequency  
PLL Clock Output Duty Cycle  
Clock Output Rise Time  
-
75  
52  
3.0  
3.0  
150  
MHz  
%
Measured at VD/2  
20% to 80% of VD  
80% to 20% of VD  
(Note 4)  
48  
-
50  
1.7  
1.7  
70  
tOR  
ns  
Clock Output Fall Time  
tOF  
-
ns  
Period Jitter (rms)  
tJIT(rms)  
tLC  
-
ps  
PLL Lock Time - CLK_IN (Note 5)  
fCLK_IN < 200 kHz  
fCLK_IN > 200 kHz  
-
-
100  
1
200  
2
UI  
ms  
PLL Lock Time - REF_CLK  
tLR  
ferr  
fREF_CLK = 8 to 75 MHz  
-
1
2
ms  
High Resolution  
High Multiplication  
0
0
-
-
±0.5  
±112  
ppm  
ppm  
Output Frequency Synthesis Resolution (Note 6)  
Notes: 4. Sample size = 10,000 points; AuxOutSrc[1:0] = 11.  
5. 1 UI (unit interval) corresponds to T or 1/f  
.
CLK_IN  
CLK_IN  
6. The frequency accuracy of the PLL clock output is directly proportional to the frequency accuracy of the  
reference clock.  
DS761A2  
7