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CS2000-CP-DZZ 参数 Datasheet PDF下载

CS2000-CP-DZZ图片预览
型号: CS2000-CP-DZZ
PDF下载: 下载PDF文件 查看货源
内容描述: [PHASE LOCKED LOOP, 75MHz, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10]
分类和应用: 光电二极管
文件页数/大小: 32 页 / 594 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS2000-CP  
5. APPLICATIONS  
5.1  
Timing Reference Clock Input  
The low jitter timing reference clock (RefClk) can be provided by either an external reference clock or an  
external crystal in conjunction with the internal oscillator. In order to maintain a stable and low-jitter PLL out-  
put the timing reference clock must also be stable and low-jitter; the quality of the timing reference clock  
directly affects the performance of the PLL and hence the quality of the PLL output.  
5.1.1  
Internal Timing Reference Clock Divider  
The Internal Timing Reference Clock (SysClk) has a smaller maximum frequency than what is allowed on  
the XTI/REF_CLK pin. The CS2000 supports the wider external frequency range by offering an internal  
divider for RefClk. The RefClkDiv[1:0] bits should be set such that SysClk, the divided RefClk, then falls  
within the valid range as indicated in Figure 7.  
Timing Reference  
Internal Timing  
Clock Divider  
Fractional-N  
Frequency  
Synthesizer  
Reference Clock  
Timing Reference Clock  
÷1  
÷2  
÷4  
XTI/REF_CLK  
PLL Output  
50 MHz (XTI)  
8 MHz < RefClk <  
8 MHz < SysClk < 18.75 MHz  
75 MHz (REF_CLK)  
N
RefClkDiv[1:0]  
Figure 7. Internal Timing Reference Clock Divider  
It should be noted that the maximum allowable input frequency of the XTI/REF_CLK pin is dependent  
upon its configuration as either a crystal connection or external clock input. See the “AC Electrical Char-  
acteristics” on page 7 for more details.  
Referenced Control  
Register Location  
RefClkDiv[1:0] .......................“Reference Clock Input Divider (RefClkDiv[1:0])” on page 28  
5.1.2  
Crystal Connections (XTI and XTO)  
An external crystal may be used to generate RefClk. To accomplish this, a 20 pF fundamental mode par-  
allel resonant crystal must be connected between the XTI and XTO pins as shown in Figure 8. As shown,  
nothing other than the crystal and its load capacitors should be connected to XTI and XTO. Please refer  
to the “AC Electrical Characteristics” on page 7 for the allowed crystal frequency range.  
XTI  
XTO  
40 pF  
40 pF  
Figure 8. External Component Requirements for Crystal Circuit  
12  
DS761A2