CobraNet Hardware User’s Manual
Pinout and Signal Descriptions
4.1 CS1810xx & CS4961xx Package Pinouts
4.1.1 CS1810xx/CS4961xx Pinout
Table 1 lists the pinout for the 144-pin LQFP CS1810xx/CS4961xx device. The interfaces
for these signals are expanded in the following sections.
Table 1. CS1810xx/CS4961xx Pin Assignments
Pin #
Pin Name
Pin #
Pin Name
Pin #
Pin Name
Pin #
Pin Name
1
2
3
4
5
6
7
8
9
VCXO_CTRL
MCLK_SEL
DBDA
37
DATA1
73
VDDIO
109
HADDR1
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
WE
74
ADDR10
ADDR14
GND
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
HADDR0
HDATA7
HDATA6
VDDIO
HDATA5
HDATA4
GND
DATA0
DATA15
DATA14
DATA13
DATA12
VDDIO
DATA11
DATA10
GND
75
DBCK
76
NC
77
ADDR13
NC
NC
78
NC
79
NC
DAO_MCLK
TEST
80
NC
81
NC
HDATA3
HDATA2
VDDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VDDD
82
ADDR15
VDDD
ADDR16
ADDR17
GND
HS3
83
NC
DATA9
DATA8
NC
84
HDATA1
HDATA0
GND
GND
85
DAO2_LRCLK
DAO1_DATA3
DAO1_DATA2/HS2
DAO1_DATA1/HS1
VDDIO
86
NC
87
ADDR18
ADDR19
OE
XTAL_OUT
XTO
NC
88
NC
89
XTI
VDDD
ADDR12
ADDR11
GND
90
CS1
GND_a
FILT2
DAO1_DATA0/HS0
DAO1_SCLK
GND
91
VDDIO
MUTE
HRESET
GND
92
FILT1
93
VDDA
DAO1_LRCLK
UART_TX_OE
VDDD
ADDR9
ADDR8
VDDIO
ADDR7
ADDR6
GND
94
VDDD
95
WATCHDOG
IOWAIT
REFCLK_IN
VDDD
GPIO0
GPIO1
GND
DAI1_DATA3
DAI1_DATA2
GND
96
UART_TXD
UART_RXD
GND
97
98
DAI1_DATA1
DAI1_DATA0
VDDIO
DAI1_SCLK
DAI1_LRCLK
GND
99
NC
ADDR5
CS2
100
101
102
103
104
105
106
107
108
DATA7
DATA6
VDDD
ADDR4
ADDR3
GND
HACK
DATA5
HDS
DATA4
HEN
HREQ
VDDIO
HADDR3
HADDR2
HR/W
NC
DATA3
ADDR2
ADDR1
ADDR0
NC
DATA2
IRQ1
GND
GPIO2
IRQ2
10
©Copyright 2005 Cirrus Logic, Inc.
DS651UM23
Version 2.3
CIRRUS [ CIRRUS LOGIC ]
