CobraNet Hardware User’s Manual
Digital Audio Interface
6.0 Digital Audio Interface
The CS18101x/CS49611x, CS18102x/CS49612x, and CM-2 support four bi-directional
synchronous serial interfaces. The CS18100x & CS49610x support one bi-directional
synchronous serial interface. All interfaces operate in master mode with DAO1_SCLK as
the bit clock and FS1 as the frame clock. A sample period worth of synchronous serial
data includes two (or four) audio channels. CobraNet supports two synchronous serial bit
rates: 48 Khz and 96 KHz. However, 96 kHz sample rate is not available when using
CS18102x/CS49612x with 16X16 channels. Bit rate is selected by the modeRateControl
variable. All synchronous serial interfaces operate from a common clock at the same bit
rate.
FS1
DAO 1_DATA0 / DAI1_DATA0
*DAO 1_DATA1 / DAI1_DATA1
*DAO 1_DATA2 / DAI1_DATA2
*DAO 1_DATA3 / DAI1_DATA3
* Not present in CS18100x or CS49610x.
1
3
5
7
2
4
6
8
Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) - CS18100x/CS49610x &
CS18101x/CS49611x
FS1
DAO1_DATA0 / DAI1_DATA0
DAO1_DATA1 / DAI1_DATA1
DAO1_DATA2 / DAI1_DATA2
DAO1_DATA3 / DAI1_DATA3
1
5
2
6
3
7
4
8
9
10
14
11
15
12
16
13
Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) - CS18102x/CS49612x
Default channel ordering is shown above. Note that the first channel always begins after
the rising or falling edge of FS1 (depending on the mode).
DAI1_SCLK period depends on the sample rate selected. Up to 32 significant bits are
received and buffered by the DSP for synchronous inputs. Up to 32 significant bits are
transmitted by the DSP for synchronous outputs. Bit 31 is always the most significant
(sign) bit. A 16-bit audio source must drive to bit periods 31-16 with audio data and bits
15-0 should be actively driven with either a dither signal or zeros. Cirrus Logic
recommends driving unused LS bits to zero.
DS651UM23
Version 2.3
©Copyright 2005 Cirrus Logic, Inc.
19
CIRRUS [ CIRRUS LOGIC ]
