CobraNet Hardware User’s Manual
Pinout and Signal Descriptions
4.2.3 Synchronous Serial (Audio) Signals
The synchronous serial interfaces are used to bring digital audio into and out of the
system. Typically the synchronous serial is wired to ADCs and/or DACs. Detailed timing
and format is described in "Digital Audio Interface" on page 19.
CM-2
Pin #
CS1810xx/
CS4961xx Pin #
Signal
Description
Direction
Notes
Synchronous serial bit clock.
64 FS for CS18100x & CS49610x (2x1 channel)
64 FS for CS18101x & CS49611x (2x4
channels)
DAO1_SCLK
Audio Bit Clock
Out
J3:A7
20
128 FS for CS18102x & CS49612x (4x4
channels)
Typically tied to DAI1_SCLK.
Output synchronous serial audio data
DAO1_DATA[3:1] not used for CS18100x &
CS49610x.
Audio Output
Data
J3:A18,
B18
DAO1_DATA[3:0]
Out
15-17, 19
Input synchronous serial audio data
131, 132, 134, 135 DAI1_DATA[3:1] not used for CS18100x &
CS49610x.
J3:
A[15:12]
DAI1_DATA[3:0]
DAI1_SCLK
Audio Input Data
Audio Bit Clock
In
In
Should be tied to DAO1_SCLK.
Synchronous serial bit clock.
J4:A7
137
4.2.4 Audio Clock Signals
See "Synchronization" on page 17 for an overview of synchronization modes and issues.
CM-2
Pin #
CS1810xx/
CS4961xx Pin #
Signal
Description
Direction
Notes
Sample clock
input
DAI1_LRCLK
In
138
22
Should be tied to DAO1_LRCLK for all devices.
DAO1_LRCLK
(FS1)
Sample clock
output
FS1 (word clock) for CS18100x/CS49610x and
CS18101x/CS49611x.
Out
Out
J3:A3
J3:A3
DAO2_LRCLK
(FS1)
Sample clock
output
14
FS1 (word clock) for CS18102x & CS49612x.
Clock input for synchronizing network to an
external clock source, for redundancy control
and synchronization of FS divider chain to
external source. See "Synchronization" on
page 17 for more detail.
REFCLK_IN
Reference clock
In
J3:A6
97
For systems featuring multiple CobraNet
interfaces operating off a common master
clock. See "Synchronization" on page 17 for
more detail.
Master audio
clock input
MCLK_IN
In
J3:A5
J3:A4
8*
8*
Master audio
clock output
MCLK_OUT
Out
Low jitter 24.576 MHz master audio clock.
*An external multiplexor controlled by this pin is required for full MCLK_IN and MCLK out
implementation.
DS651UM23
Version 2.3
©Copyright 2005 Cirrus Logic, Inc.
13
CIRRUS [ CIRRUS LOGIC ]
