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CS1601 参数 Datasheet PDF下载

CS1601图片预览
型号: CS1601
PDF下载: 下载PDF文件 查看货源
内容描述: 数字PFC控制器,用于电子镇流器 [Digital PFC Controller for Electronic Ballasts]
分类和应用: 功率因数校正电子控制器
文件页数/大小: 16 页 / 789 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS1601  
5.2 Startup vs. Normal Operation Mode  
5.4 Output Power and PFC Boost Inductor  
The CS1601 has two discrete operation modes: startup and  
normal. Startup mode will be activated when Vlink is less than  
90% of nominal value, VO(startup) and remains active until Vlink  
reaches 100% of nominal value, as shown in Figure 15.  
Startup mode is activated during initial system power-up. Any  
Vlink drop to less than VO(startup), such as a load change, can  
cause the system to enter startup mode until Vlink is brought  
back into regulation.  
In normal operating mode, the nominal output power is  
estimated by the following equation.  
V
V
link inmin2  
V
---------------------------------------------------------  
=      inmin   
2
[Eq.1]  
P
o
2 fmax LBVlink  
where:  
Po  
rated output power of the system  
efficiency of the boost converter (estimated as 100%  
by the PFC algorithm)  
V
[V]  
link  
Vin(min) minimum RMS line voltage measured after the  
rectifier and EMI filter. Vin(min) is equal to 90Vrms or  
108Vrms depending on the AC Line Voltage  
operating range.  
100%  
90%  
Normal  
Mode  
Normal  
Mode  
Vlink  
nominal PFC output voltage; Vlink = 400V when  
Vin(min) = 90 Vrms or Vlink = 460 V when  
Vin(min) = 108Vrms  
fmax  
maximum switching frequency; for the CS1601  
fmax = 70kHz and the CS1601H fmax = 100kHz  
t[ms]  
Figure 15. Startup and Normal Modes  
LB  
boost inductor specified by rated power requirement  
Startup mode is defined as a surge of current delivering  
maximum power to the output regardless of the load. During  
every active switch cycle, the 'ON' time is calculated to drive a  
constant peak current over the entire line cycle. However, the  
'OFF' time is calculated based on the DCM/CCM boundary  
equation.  
  
margin factor to guarantee rated output power (Po)  
against boost inductor tolerances.  
Equation 1 is provided for explanation purposes only. Using  
substituted required design values for Vlink and fmax gives the  
following equation:  
2
460V 108V 2  
2 70kHz LB460V  
------------------------------------------------------------  
P
=     108V   
[Eq.2]  
5.3 Burst Mode  
o
Burst mode is utilized to improve system efficiency when the  
system output power (Po) is <5% of nominal. Burst mode is  
implemented by intermittently disabling the PFC over a full  
half-line period under light-load conditions, as shown in  
Figure 16.  
Changing the value for the Vlink voltage is not recommended.  
Solving Equation 2 for the PFC boost inductor LB gives the  
following equation:  
2
460V 108V 2  
------------------------------------------------------------  
[Eq.3]  
LB =     108V   
Po  
[W]  
2 70kHz P 460V  
o
If a value of the boost inductor other than that obtained from  
Equation 3 above is used, the total output power capability as  
well as the minimum input voltage threshold will differ  
according to Equation 2. Note that if the input voltage drops  
below 108Vrms and the inductance value is <LB, the link  
voltage Vlink will drop below 460V and fall out of regulation.  
Burst Threshold  
Burst Mode  
Active  
t [ms]  
Vin  
[V]  
PFC  
Vin  
FET  
Vgs  
Disable  
L < LB   
L = LB  
t [ms]  
L > LB  
Figure 16. Burst Modes  
108  
305  
VAC(rms)  
Figure 17. Relative Effects of Varying Boost Inductance  
10  
DS931PP6