CL-PS7500FE
System-on-a-Chip for Internet Appliance
12.7.2 Pedestal Current
The DACs can be programmed to generate a pedestal offset of 20 LSB-equivalent currents. These are
controlled individually with pedon[2:0] (EREG[10:8]), though they are typically programmed on or off
together, depending on the monitor characteristics: pedon[0] controls the red pedestal; pedon[1] the
green pedestal; pedon[2] the blue pedestal. If pedon[n] is high, the pedestal current switches on as the
border starts and turns off as the border ends.
12.7.3 Video DAC Currents
The DACs are each 8-bit resolution and source 256 units of current according to the digital value from the
video MUX. The current step is set by a common reference current, VIREF. The recommended reference
current is 0.56 mA. This allows a DAC step of 69 µA. The digital value 0 gives 0 current and the digital
value ‘0xFF’ gives an output current of 255 × 69 = 17.6 mA. If EREG[10:8] is set during display time, the
digital value 0 generates 20 × 69 = 1.38 mA, and the digital value ‘0xFF’ generates 275 × 69 = 18.98 mA.
A 4.3-kΩ resistor connected between VIREF and V provides the desired 0.56 mA at 2.6 V.
DD
DAC Accuracy
At 120 MHz, the DACs are accurate to 8-bits absolute resolution. They are always monotonic.
12.7.4 Monochrome Output
The CL-PS7500FE does not generate a separate composite monochrome signal. If required, this can be
generated by resistively mixing the R, G, and B externally.
132
June 1997
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