CL-PS7500FE
System-on-a-Chip for Internet Appliance
12.6.1 ECLK
ECLK is output along with the data ED[7:0], so that the data can be externally latched and MUX’ed. ECLK
is controlled by EREG[13] and EREG[2]. If EREG[2] is ‘0’, then ECLK is output as logic 0. This is the
power-saving configuration whenever ECLK is not required. If EREG[2] is ‘1’ and EREG[13] is ‘0’, ECLK
is the PIXCLK output synchronously with the data stream. If EREG[13] is ‘1’, then ECLK is the LCD clock
that runs at one quarter the pixel rate.The LCD clock is only enabled while horizontal display data is being
output and is synchronous to the data stream.
12.6.2 Power Saving Considerations
The External port can be configured to minimize power usage. It is very important not to load the signals
heavily, especially ECLK that can clock at the pixel rate.When it is not in use, ECLK should not output the
raw pixel data, but should output static signals. This is done by selecting EREG[1:0] = 3 and setting all
entries of the Ext LUT to be one value. Turn off ECLK by setting EREG[2] to ‘0’.
If an LCD is fitted, but not operated, it may be necessary to power down the input signals to it. This can
be achieved by setting EREG[13] low, disabling the grayscaler, and by disabling the external port as
described above.
12.6.3 Vertical and Horizontal Synchronization
Software control over the polarities of the synchronization pulses is provided.Two types of composite sync
signals can be output, each of either polarity. The logical OR of the horizontal and vertical syncs can be
output on the HSYNC pin; the XOR of can be output on the VSYNC pin. Equalization pulses in the com-
posite synchronization signal are supported for Interlace mode.When LCD mode is selected, the external
HSYNC and VSYNC pulses are modified to the requirements of an LCD screen.
The HSYNC and VSYNC pins are programmed with EREG[19:16].
12.6.4 GENLOCK
GENLOCK is supported by the CL-PS7500FE. The SYNC pin can reset the vertical counter to the first
raster (SYNC).
12.7 Analog Outputs
The CL-PS7500FE outputs analog R, G, and B signals. It is designed to drive doubly-terminated, 75-Ω
lines directly.
12.7.1 DAC Control
There are four control bits in the Ext register associated with the DACs. These are EREG[12] and
EREG[10:8] (pedon[2:0]).
Power-Save Mode
When EREG[12] is high, the DACs are enabled and generate a current proportional to the digital values
from the video MUX.When EREG[12] is low, the reference current into all three DACs is turned off, so the
DACs generate no output current, consuming much less power. This is useful when operating in LCD
mode or at any time the screen should be blanked.
June 1997
131
ADVANCE DATA BOOK v2.0
VIDEO FEATURES
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