CL-PD6710/’22
ISA–to–PC-Card Host Adapters
2.1 Pin Diagrams
IRQ3
SA7
IRQ4
SA8
IRQ5
SA9
SA10
IRQ7
SA11
SA12
REFRESH*
SA13
SA14
SA15
SA16
IOR*
IOW*
AEN
IOCHRDY
GND
SD0
SD1
ZWS*
SD2
GND
SD3
ISA_VCC
SD4
SD5
IRQ9
SD6
SD7
PWRGOOD
SPKR_OUT*/C_SEL
-INTR
N/C
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
SA6
SA5
SA4
ALE
SA3
SA2
CLK
SA1
SA0
MEMCS16*
SBHE*
IOCS16*
LA23
IRQ10
LA22
IRQ11
LA21
CORE_VDD
IRQ12/LED_OUT*
LA20
IRQ15/RI_OUT*
LA19
IRQ14
LA18
LA17
MEMR*
MEMW*
SD8
SD9
SD10
GND
SD11
ISA_VCC
SD12
SD13
SD14
ISA_VCC
CL-PD6710
144-Pin VQFP
+5V
SOCKET_VCC
GND
SD15
-CD2
WP/-IOIS16
D10
D2
D9
D1
D8
D0
BVD1/-STSCHG/-RI
A0
BVD2/-SPKR/-LED
A1
A2
-INPACK
A3
-WAIT
GND
A4
SOCKET_VCC
RESET
A5
A6
A25
A7
A24
A12
A23
A15
A22
A16
A21
RDY/-IREQ
A20
-WE
May 1997
+5V
VPP_PGM
VPP_VCC
-VPP_VALID
-VCC_3
-VCC_5
5V_DET
-REG
D3
-CD1
D4
D11
D5
D12
D6
CORE_VDD
D13
SOCKET_VCC
D7
GND
D14
-CE1
D15
A10
-CE2
-OE
A11
-IORD
A9
-IOWR
A8
A17
A13
A18
A14
A19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Figure 2-1. CL-PD6710 Pin Diagram
PRELIMINARY DATA SHEET v3.1
PIN INFORMATION
9
CIRRUS [ CIRRUS LOGIC ]
