CL-PD6710/’22
ISA–to–PC-Card Host Adapters
Table 2-1. ISA Bus Interface Pins (cont.)
Pin Number
Pin Name
Description
Qty. I/O Pwr. Drive
CL-PD6710 CL-PD6722
PWRGOOD
Power Good: The CL-PD67XX will be reset 141
when the POWERGOOD input is low. Connect
to the POWERGOOD signal from the system
power supply; or, if not available, connect to
inverted RESETDRV signal from ISA bus.
201
1
1
1
I
4
4
4
–
AEN
Address Enable: This is an input from the 126
host CPU bus signal that distinguishes
between DMA and non-DMA bus cycles. This
input should be high for a DMA cycle and will
cause the CL-PD67XX to ignore IOR* and
IOW* except when a CL-PD6722 is configured
for DMA and its DREQ (IRQ10) and DACK*
(IRQ9) signals are active. Connect to ISA sig-
nal AEN.
187
I
–
When CL-PD67XX is in Suspend mode (see
Misc Control 2, bit 2 on page 61), pull this input
high during system power-down for lowest
power consumption.
MEMCS16*
IOCS16*
Memory Select 16: This output is an acknowl- 99
edge of 16-bit-wide access support and is gen-
erated by the CL-PD67XX when a valid 16-bit-
word-accessible memory address has been
decoded. Connect to ISA signal MEMCS16*.
160
158
O-
OD
16
mA
I/O Select 16: This output is an acknowledge 97
for 16-bit-wide access support and is gener-
ated by the CL-PD67XX when a valid 16-bit
word accessible I/O address has been
decoded. Connect to ISA signal IOCS16*.
O-
OD
16
mA
1
1
4
4
IOCHRDY
I/O Channel Ready: This output is driven low 127
by the CL-PD67XX to lengthen host cycles.
Connect to the ISA bus IOCHRDY signal.
188
O-
TS
16
mA
IRQ[14, 11,
7, 5:3]
Interrupt Request: These outputs indicate 86, 93, 116,
148, 154, 177,
programmable interrupt requests generated 113, 111, 109 174, 172, 170
from any of a number of card actions. Although
there is no specific mapping requirement for
connecting interrupt lines from the
CL-PD67XX to the system, a common use is
to connect these pins to the corresponding ISA
signal names in the system.
O-
TS
6
4
2 mA
IRQ9
Interrupt Request 9: In default mode this out- 138
put indicates an interrupt request from one of
the cards.
198
When the CL-PD6722 is in DMA mode (see
Misc Control 2, bit 6), IRQ9 becomes an input
and is connected to the ISA bus DACK* line
corresponding to the ISA bus DREQ line that
the IRQ10 pin is connected to. In DMA mode
this signal is active-low.
I/O-
TS
1
4
2 mA
May 1997
13
PRELIMINARY DATA SHEET v3.1
PIN INFORMATION
CIRRUS [ CIRRUS LOGIC ]
