CL-PD6710/’22
ISA–to–PC-Card Host Adapters
Table of Contents
7.6 Card I/O Map 0–1 Offset Address Low............52
7.7 Card I/O Map 0–1 Offset Address High ...........52
1. GENERAL CONVENTIONS.................. 7
2. PIN INFORMATION............................... 8
2.1 Pin Diagrams .....................................................9
2.2 Pin Description Conventions............................11
2.3 Pin Descriptions...............................................12
2.4 Power-On Configuration Summary..................21
8. MEMORY WINDOW MAPPING
REGISTERS .........................................53
8.1 System Memory Map 0–4 Start Address
Low ..................................................................53
8.2 System Memory Map 0–4 Start Address
High..................................................................54
8.3 System Memory Map 0–4 End Address
Low ..................................................................54
8.4 System Memory Map 0–4 End Address
High..................................................................55
8.5 Card Memory Map 0–4 Offset Address
Low ..................................................................56
8.6 Card Memory Map 0–4 Offset Address
High..................................................................56
3. INTRODUCTION.................................. 22
3.1 System Architecture.........................................22
3.1.1 PC Card Basics ............................................22
3.1.2 CL-PD67XX Windowing Capabilities............22
3.1.3 CL-PD67XX Functional Blocks.....................25
3.1.4 Interrupts ......................................................25
3.1.5 Alternate Functions of Interrupt Pins............26
3.1.6 General-Purpose Strobe Feature .................26
3.1.7 Voltage Sense Pins.......................................27
3.1.8 CL-PD67XX Power Management .................27
3.1.9 Socket Power Management Features...........28
3.1.10 Write FIFO....................................................29
3.1.11 Bus Sizing.....................................................29
3.1.12 Programmable PC Card Timing....................29
3.1.13 ATA Mode Operation.....................................29
9. EXTENSION REGISTERS...................58
9.1 Misc Control 1..................................................58
9.2 FIFO Control ....................................................60
9.3 Misc Control 2..................................................61
9.4 Chip Information...............................................63
9.5 ATA Control ......................................................64
9.6 Extended Index................................................65
9.7 Extended Data .................................................65
9.7.1 Data Mask 0–1 .............................................66
9.7.2 Extension Control 1 (CL-PD6722 only,
formerly DMA Control)..................................66
9.7.3 Maximum DMA Acknowledge Delay
(CL-PD6722 only).........................................67
3.1.14 DMA Mode Operation for
the CL-PD6722.............................................30
3.1.15 Selective Data Drive for I/O Windows...........30
3.2 Host Access to Registers.................................30
3.3 Power-On Setup...............................................31
4. REGISTER DESCRIPTION
9.7.4 External Data (CL-PD6722 only, Socket A,
Index 2Fh).....................................................69
9.7.5 External Data (CL-PD6722 only, Socket A,
Index 6Fh).....................................................70
CONVENTIONS................................... 32
5. OPERATION REGISTERS.................. 33
5.1 Index ................................................................33
5.2 Data .................................................................36
9.7.6 Extension Control 2 (CL-PD6722 only) ........71
6. CHIP CONTROL REGISTERS............ 37
6.1 Chip Revision...................................................37
6.2 Interface Status................................................38
6.3 Power Control ..................................................40
6.4 Interrupt and General Control..........................42
6.5 Card Status Change ........................................44
6.6 Management Interrupt Configuration...............45
6.7 Mapping Enable...............................................47
10. TIMING REGISTERS ...........................72
10.1 Setup Timing 0–1.............................................72
10.2 Command Timing 0–1......................................73
10.3 Recovery Timing 0–1 .......................................74
11. ATA MODE OPERATION.....................75
12. USING GPSTB PINS FOR EXTERNAL
PORT CONTROL (CL-PD6722 only)..77
12.1 Control of GPSTB Pins ....................................77
12.2 Example Implementations of GPSTB-Controlled
Read and Write Ports.......................................79
12.3 GPSTB in Suspend Mode................................80
7. I/O WINDOW MAPPING
REGISTERS ........................................ 49
7.1 I/O Window Control..........................................49
7.2 System I/O Map 0–1 Start Address Low..........50
7.3 System I/O Map 0–1 Start Address High.........50
7.4 System I/O Map 0–1 End Address Low...........51
7.5 System I/O Map 0–1 End Address High..........51
13. VS1# AND VS2# VOLTAGE
DETECTION .........................................81
May 1997
3
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