CL-PD6710/’22
ISA–to–PC-Card Host Adapters
INDEX
Card I/O Map 0–1 Address Offset Low registers 52
Card IRQ Select bits 42
Card Is I/O bit 42
Card Memory Map 0–4 Offset Address High
registers 56
Card Memory Map 0–4 Offset Address Low
registers 56
Card Power On bit 39
Numerics
+5V 20
5V Core bit 61
A
A[25:0] 16
A_ pin name 16
See also the pin name
A21 bit 64
A22 bit 64
A23/VU bit 64
A24/M/S* bit 64
A25/CSEL bit 64
AC specifications 91–109
Active-high GPSTB bit 71
AEN 13
Card Reset* bit 43
Card Status Change register 44
Card Timer Select bits 55
-CD[2:1] 18
-CE[2:1] 18
Chip Identification bits. See Cirrus Logic Host-Adapter
Identification bits
Chip Information register 63
Chip Revision register 37
Cirrus Logic Host-Adapter Identification bits 63
CLK 15
CL-PD67XX Revision Level bits 63
Command Multiplier Value bits 73
Command Prescalar Select bits 73
Command Timing 0–1 registers 73
conventions
ALE 12
ATA Control register 64
ATA mode
description 75
overview 29
pin cross reference 75
ATA Mode bit 64
Auto Power Clear Disable bit 66
Auto-Power bit 41
Auto-Size I/O Window 0 bit 49
Auto-Size I/O Window 1 bit 49
bit naming 32
general 7
numbers and units 7
pin naming 11
register headings 32
CORE_VDD 20
B
B_ pin name 16
D
See also the pin name
Battery Dead Or Status Change bit 44
Battery Dead Or Status Change Enable bit 45
Battery Voltage Detect bits 38
Battery Warning Change bit 44
Battery Warning Enable bit 45
BBS (bulletin board system) 114
bus sizing 29
BVD1/-STSCHG/-RI 19
BVD2/-SPKR/-LED 18
Bypass Frequency Synthesizer bit 61
D[15:0] 16
Data Mask 0–1 register 66
Data Mask Select 0–1 bits 66
Data register 36
DC specifications 87–90
Device Index bit 33
DMA Control register. See Extension Control 1 register
DMA Enable bits 67
DMA mode
configuring 84–86
description 83
C
overview 30
C_SEL 15
Card Detect bits 38
Card Detect Change bit 44
Card Detect Enable bit 45
Card Enable bit 41
DMA Read Cycle timing 105
DMA Request timing 109
DMA System bit 62
DMA Write Cycle timing 107
Drive LED Enable bit 61
Dual/Single Socket* bit 63
Card I/O Map 0–1 Address Offset High registers 52
124
May 1997
INDEX
PRELIMINARY DATA SHEET v3.1
CIRRUS [ CIRRUS LOGIC ]
