CL-PD6710/’22
ISA–to–PC-Card Host Adapters
Register Name: System Memory Map 0–4 End Address High
Index: 13h, 1Bh, 23h, 2Bh, 33h
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Card Timer Select
RW:00
Scratchpad Bits
End Address 23:20
RW:0000
RW:00
Register Name: Card Memory Map 0–4 Offset Address Low
Index: 14h, 1Ch, 24h, 2Ch, 34h
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Offset Address 19:12
RW:00000000
Register Name: Card Memory Map 0–4 Offset Address High
Index: 15h, 1Dh, 25h, 2Dh, 35h
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write Protect REG Setting
Offset Address 25:20
RW:000000
RW:0
RW:0
B.5 Extension Registers
Register Name: Misc Control 1
Index: 16h
Register Per: socket
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
5 V Detect
(CL-PD6710)
Pulse
Management
Interrupt
Speaker
Enable
Pulse System
IRQ
Inpack Enable
RW:0
Scratchpad Bits
V
3.3V
CC
Reserved
(CL-PD6722)
RW:00
RW:0
RW:0
RW:0
RW:0
R:X W:0
Register Name: FIFO Control
Index: 17h
Register Per: socket
Register Compatibility Type: ext.
Bit 2 Bit 1 Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Empty Write
FIFO
a
Scratchpad Bits
RW:0000000
RW
a
Because a write will flush the FIFO, these scratchpad bits should be used only when card activity is guaranteed not to occur.
120
May 1997
PRELIMINARY DATA SHEET v3.1
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