CS8406
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(Inputs: Logic 0 = 0 V, Logic 1 = VL; C
L
= 20 pF)
Parameter
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Symbol
f
sck
t
csh
t
css
t
scl
t
sch
t
dsu
t
dh
t
pd
t
r1
t
f1
t
r2
t
f2
Min
0
1.0
20
66
40
15
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
Max
6.0
-
-
-
-
-
50
25
25
100
100
Units
MHz
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX ((1/256 F
S
+ 8), 66)
Notes:
9. If Fs is lower than 51.850 kHz, the maximum CCLK frequency should be less than 115 Fs. This is dic-
tated by the timing requirements necessary to access the Channel Status and User Bit buffer memory.
Access to the control register file can be carried out at the full 6 MHz rate.
10. T
sch
must be greater than the larger of the two values, either 1/256FS + 8 ns, or 66 ns.
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For f
sck
< 1 MHz.
CS
t css
CCLK
t r2
CDIN
t dsu
t dh
t f2
t scl
t sch
t csh
t pd
CDOUT
Figure 3. SPI Mode Timing
DS580F5
7
CIRRUS [ CIRRUS LOGIC ]
