CDB61880
corresponding receiver has detected a loss of signal
condition. Refer to the CS61880 Data Sheet for
LOS conditions.
2.13 Digital Signal Connections
There are eight fourteen pin bed stake headers (la-
beled J4 through J11) that provide access to the
digital signals used to interface with back-end de-
vices (framers, mappers, ASIC, etc.) and all eight
LOS signals, in both Hardware And Host mode.
Figure 10 shows the layout for one of the eight 14-
pin bed stake headers used to access the back-end
digital signals, LOS signals and the different set-
tings for the TCLK/TNEG pins.
2.15 JTAG Connection
A 5-pin bed stake header (J60) is provided to allow
easy access to the IEEE 1149.1 JTAG Boundary
Scan signals from the device.
2.16 Host Interface Connection
Connector J12 is used to connect the CS61880
evaluation board to the host computer, through a
standard 25 pin male to female parallel port cable.
No external µController board is required for host
interface connection. This connector is used for
both serial and parallel interface.
Uni-Polar Mode Active
Bi-polar Mode
3. HOST SETUP DESCRIPTION
Place the switches shown in Table 3 to the stated
configuration before setting the Mode switch (S15)
to Serial or Parallel Host mode. Refer to Figure 4
on page 6 for switch S15 settings.
TAOS active when
Table 3. Switch Settings for Host Mode
Transmitters High-Z
MCLK present
RZ mode active when
MCLK absent
Switch
S1 through S8
S9 # 3 through # 7
S10
Position
NONE (middle)
OPEN (low)
OPEN (middle)
NC (middle)
S11
S12 through S14
OPEN (middle)
- Switches #1 and #2 inside of switch block S9
are used in Parallel Host mode to select
Motorola, Intel, multiplex or Non-multiplex
modes. Switch S9 #1 and #2 are not used in
Serial Host mode.
Figure 10. Digital Signal Control/Access
2.14 LOS Indicators
The two 4-LED packs D1 and D2 (labeled ALOS
0-7) represent the LOS signal status for LOS 0-7
pins. The ALOS 0-7 LEDs will illuminate when the
DS450DB1
9
CIRRUS [ CIRRUS LOGIC ]
