CS61577
T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol
Min
Typ
Max
Units
Crystal Frequency
TCLK Frequency
ACLKI Frequency
RCLK Duty Cycle
Rise Time, All Digital Outputs
Fall Time, All Digital Outputs
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
RDATA Valid Before RCLK Falling
RPOS/RNEG Valid Before RCLK Rising
RPOS/RNEG Valid After RCLK Falling
RDATA Valid After RCLK Falling
(Note 25)
fc
ftclk
faclki
pwh1/tpw1
tr
-
-
-
45
-
6.176000
-
-
-
55
85
85
-
-
-
-
-
MHz
MHz
MHz
%
ns
ns
ns
ns
ns
ns
1.544
1.544
50
(Note 26)
(Note 27)
(Note 28)
(Note 28)
t
-
-
-
-
tf
tsu2
th2
tsu1
tsu1
tsu1
th1
-
25
25
150
150
150
150
150
150
(Note 29)
(Note 30)
(Note 31)
(Note 29)
(Note 30)
(Note 31)
274
274
274
274
274
274
ns
ns
ns
ns
-
-
-
th1
th1
RPOS/RNEG Valid After RCLK Rising
Notes: 25. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.
26. ACLKI provided by an external source or TCLK.
27. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached.
28. At max load of 1.6 mA and 50 pF.
29. Host Mode (CLKE = 1).
30. Extended Hardware Mode.
31. Hardware Mode, or Host Mode (CLKE = 0)
32. The transmitted pulse width does not depend on the TCLK duty cycle.
E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol
Min
Typ
Max
Units
Crystal Frequency
TCLK Frequency
TCLK Duty Cycle for LEN2/1/0 = 0/0/0
ACLKI Frequency
RCLK Duty Cycle
Rise Time, All Digital Outputs
(Note 25)
fc
ftclk
pwh2/tpw2
faclki
pwh1/tpw1
tr
-
-
40
-
45
-
8.192000
2.048
50
2.048
50
-
-
60
-
55
85
85
-
-
-
-
-
MHz
MHz
%
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 32)
(Note 26)
(Note 27)
(Note 28)
(Note 28)
t
t
-
-
-
-
Fall Time, All Digital Outputs
tf
tsu2
th2
tsu1
tsu1
tsu1
th1
-
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
RDATA Valid Before RCLK Falling
RPOS/RNEG Valid Before RCLK Rising
RPOS/RNEG Valid After RCLK Falling
RDATA Valid After RCLK Falling
RPOS/RNEG Valid After RCLK Rising
25
25
100
100
100
100
100
100
(Note 29)
(Note 30)
(Note 31)
(Note 29)
(Note 30)
(Note 31)
194
194
194
194
194
194
-
-
-
th1
th1
DS155PP2
5
CIRRUS [ CIRRUS LOGIC ]
