CDB5560-2
3.4
Digital Section
3.4.1
Hardware Configuration
The CDB5560-2 evaluation board hardware comes pre-configured so the only connection required
between it and a data acquisition system is the serial port connection.
The hardware setup is reconfigurable through the hardware control interface connectors. Configure the
evaluation board by setting the appropriate control line to the appropriate logic level.
Table 3. Hardware Configuration Signals
Function
Analog Input Buffers
Serial Port Mode
Default Level
Buffers = Enabled (High)
Label
BUFEN
SMODE
RDY
Connector
J1
Test Point
J3, Pin1
J3, Pin 3
J3, Pin 4
J3, Pin 6
J3, Pin 7
J3, Pin 8
J3, Pin 9
E23
Sync. Self Clock = Enabled (High)
Data Ready When Set (Low)
Reset = Inactive (High)
J6, Pin 12
J8, Pin 10
J6, Pin 6; S1
J6, Pin 8; J2
J6, Pin 2
J6, Pin 4
J8, Pin 2
J8, Pin 12
Data Ready Flag
Reset
RST
Self Calibration Mode
Bipolar / Unipolar Mode
Sleep Mode
Calibration = Inactive (Low)
Bipolar = Enabled (High)
CAL
BP / UP
SLEEP
CS
Sleep = Inactive (High)
Serial Port Communication
Data Conversion Mode
Chip Select = Enabled (Low)
Continuous Conversion = Active (Low)
CONV
E21
3.4.2
SPI™ Serial Port Communications
The CS5560 ADC communications port features an SPI™ serial port. It can be configured for SSC mode
(Master) or SEC mode (Slave) mode as shown in Table 4. Test points are provided to monitor serial com-
munications.
Connections to the serial interface are made according to the following table.
Table 4. Serial Interface Connections
Function
Chip Select
Label
CS
Connector
J8, Pin 2
J8, Pin 4
J8, Pin 6
J8, Pin 8
Test Point
E23
Serial Data Input
Serial Data Output
Serial Clock
SDI
E24
SDO
SCLK
E25
E26
DS790DB2
9
CIRRUS [ CIRRUS LOGIC ]
