CS5361
4.2.2 Master Mode
In Master mode, LRCK and SCLK operate as outputs. The left/right and serial clocks are internally derived from the
master clock with the left/right clock equal to Fs and the serial clock equal to 64x Fs, as shown in Figure 23. Refer
to Table 3 for common master clock frequencies.
Single
Speed
÷ 256
÷ 128
÷ 64
00
Double
Speed
LRCK Output
(Equal to Fs)
01
10
Quad
Speed
÷ 1
÷ 2
0
1
M1 M0
00
MCLK
Single
Speed
÷ 4
÷ 2
÷ 1
MDIV
Double
Speed
SCLK Output
01
10
Quad
Speed
Figure 23. CS5361 Master Mode Clocking
MDIV = 0
MCLK (MHz)
8.192
MDIV = 1
MCLK (MHz)
16.384
SAMPLE RATE (kHz)
32
44.1
48
11.2896
12.288
22.5792
24.576
64
8.192
16.384
88.2
96
11.2896
12.288
22.5792
24.576
176.4
192
11.2896
12.288
22.5792
24.576
Table 3. CS5361 Common Master Clock Frequencies
DS467F2
17
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