CS5396 CS5397
SPI CONTROL PORT SWITCHING CHARACTERISTICS
Inputs: Logic 0 = DGND, Logic 1 = VD; C
L
= 20 pF)
Parameter
Symbol
f
sck
t
csh
t
css
t
scl
t
sch
t
dsu
(Note 7)
(Note 8)
(Note 8)
t
dh
t
r2
t
f2
Min
-
1.0
20
66
66
40
15
-
-
Max
6
-
-
-
-
-
-
100
100
Unit
MHz
µs
ns
ns
ns
ns
ns
ns
ns
(T
A
= 25 °C; VD, VA = 5V ±5%;
SPI Mode
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Notes: 7. Data must be held for sufficient time to bridge the transition time of CCLK.
8. For F
SCK
< 1 MHz.
CS
t css
CCLK
t
r2
CDIN
t scl
t
sch
t csh
t
f2
t dsu t
dh
DS229PP2
9
CIRRUS [ CIRRUS LOGIC ]
