CS5396 CS5397
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128× Oversampling Mode
GENERAL DESCRIPTION
The CS5396/97 is a 24-bit, stereo A/D converter
designed for stereo digital audio applications. The
analog input channels are simultaneously sampled
by separate, patented, 7th-order tri-level delta-sig-
ma modulators at either 128 or 64 times the output
sample rate (64× Fs or 128× Fs) of the device. The
resulting serial bit streams are digitally filtered,
yielding pairs of 24-bit values at output sample
rates (Fs) of up to 100 kHz. This technique yields
nearly ideal conversion performance independent
of input frequency and amplitude. The converter
does not require difficult-to-design or expensive
anti-alias filters, and it does not require external
sample-and-hold amplifiers or voltage references.
Only normal power supply decoupling compo-
nents, voltage reference bypass capacitors and a
single resistor and capacitor on each input for anti-
aliasing are required, as shown in Figure 1. An on-
chip voltage reference provides for a differential
input signal range of 4.0 Vpp. The device also con-
tains a high pass filter, implemented digitally after
the decimation filter, to completely eliminate any
internal offsets in the converter or any offsets
present at the input circuitry to the device. Output
data is available in serial form, coded as 2’s com-
plement 24-bit numbers. For more information on
delta-sigma modulation techniques see the refer-
ences at the end of this data sheet.
Reduction of 24-bit data to 20, 18 or 16-bit data
with psychoacoustically optimized dither
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Programmability of psychoacoustic filter coef-
ficients
Peak Input Signal Level Monitor with either
High Resolution or Bar Graph mode selection
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Signal inversion
High pass filter defeat
Mute
Access to the digital filter to allow the input of
external digital audio data to produce a two-to-
one decimated output and/or psychoacoustic bit
reduction.
STAND-ALONE MODE
Master Clock - Stand-Alone Mode
The master clock is the clock source for the delta-
sigma modulator sampling (MCLKA) and digital
filters (MCLKD). The required MCLKA/D fre-
quency is determined by the desired Fs and must be
256× Fs. Table 1 shows some common master
clock frequencies.
LRCK
(kHz)
32
MCLKA/D
(MHz)
SCLK
(MHz)
2.048
2.822
3.072
4.096
5.6448
6.144
8.192
44.1
48
64
88.2
96
11.2896
12.288
16.384
22.5792
24.576
Stand-Alone vs. Control Port Mode
The CS5396/97 can operate in either Stand-Alone
or Control Port Mode. The functionality of pins 17,
18 and 19 is established upon entering either the
Stand-Alone or Control Port mode, as described in
the Pin Description section.
Table 1. Common Clock Frequencies for Stand-Alone
Mode
Serial Data Interface - Stand-Alone Mode
The Control Port Mode requires a micro-controller
and allows access to many additional features,
which include:
The CS5396/97 supports two serial data formats
which are selected via the digital format select pin,
DFS. The digital output format determines the rela-
tionship between the serial data, left/right clock and
serial clock. Figures 2 and 3 detail the interface for-
12
DS229PP2
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