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CDB42324 参数 Datasheet PDF下载

CDB42324图片预览
型号: CDB42324
PDF下载: 下载PDF文件 查看货源
内容描述: 10式, 6手续, 2 Vrms的音频编解码器 [10-In, 6-Out, 2 Vrms Audio CODEC]
分类和应用: 解码器编解码器
文件页数/大小: 71 页 / 1231 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS42324  
Mute Control 3 (Output) - Active-low mute output can drive external circuitry to eliminate the  
clicks and pops associated with any single-rail output. This pin will become a high-impedance out-  
put during power-down mode or when an invalid MCLK to LRCK ratio is detected.  
MUTEC3  
13  
VCMBUF (Output) - Internally buffered VCMDAC  
VCMBUF  
VCMDAC  
14  
15  
DAC Common-Mode Voltage (Output) - Filter connections for the DAC internal quiescent refer-  
ence voltage.  
VA_H  
16, 18 Analog High Voltage Power (Input) - Positive power for the internal output buffer section.  
17 Analog Ground (Input) - Ground reference for high-voltage section.  
GNDH  
AOUT1A, AOUT1B 19, 20 DAC Analog Audio Outputs (Output) - The full-scale output level is specified in the DAC Analog  
AOUT2A, AOUT2B 21, 22 Characteristics specification table.  
AOUT3A, AOUT3B 23, 24  
AIN5B, AIN5A  
AIN4B, AIN4A  
AIN3B, AIN3A  
AIN2B, AIN2A  
AIN1B, AIN1A  
25, 26 Stereo Analog Inputs 1-5 (Input) - The full-scale input level is specified in the ADC Analog Char-  
27, 28 acteristics specification table.  
29, 30  
31, 32  
33, 34  
RST  
35 Reset (Input) - The device enters a low-power mode when this pin is driven low.  
36 ADC Overflow (Output) - Indicates an ADC overflow condition is present.  
OVFL  
SDIN2  
SDIN1  
37 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.  
38  
Master Clock 2 (Input) - Optional asynchronous clock source for the DAC’s delta-sigma modula-  
tors.  
MCLK2  
LRCK2  
39  
Serial Port 2 Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is cur-  
rently active on the serial audio input data line.  
40  
SCLK2  
VD  
41 Serial Port 2 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 2.  
42 Digital Power (Input) - Positive power for the internal digital section.  
GND  
43 Digital Ground (Input) - Ground reference for the internal digital section.  
Digital Interface Power (Input) - Determines the required signal level for the control and serial  
44 port interfaces as shown in “I/O Power Rails” on page 12. Refer to the“Recommended Operating  
Conditions” on page 13 for appropriate voltages  
VL  
SDOUT  
SCLK1  
45 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.  
46 Serial Port 1 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 1.  
Serial Port 1 Left Right/Clock (Input/Output) - Determines which channel, Left or Right, is cur-  
rently active on the serial audio output data line.  
LRCK1  
MCLK1  
47  
Master Clock 1 (Input) - Clock source for the ADC’s delta-sigma modulators. By default, this sig-  
nal also clocks the DAC’s delta-sigma modulators.  
48  
DS721A6  
11