CS42324
1.2
Hardware Mode
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
OVFL
RST
M0
1
M1
2
AIN1A
AIN1B
AIN2A
AIN2B
AIN3A
AIN3B
AIN4A
AIN4B
AIN5A
AIN5B
MDIV
MUTE
DIF
3
4
5
6
7
8
32
31
30
FILT+
VCMADC
GND
CS42324
29
28
27
26
VA
9
10
VBIAS
MUTEC1
MUTEC2
11
12
25
13 14 15 16 17 18 19 20 21 22 23 24
Pin Name
#
Pin Description
M0, M1
MDIV
1, 2 Mode Selection (Input) - Determines the operational mode of the device.
MCLK Divider (Input) - Setting this pin high places a divide-by-2 circuit in the MCLK path to the
3
4
5
6
7
core device circuitry.
MUTE
DIF
MUTE (Input) - Engages the internal digital mute and activates the MUTECx pins
DIF (Input) - Sets the serial audio interface format. Setting DIF high selects I²S audio format and
low selects LJ audio format.
FILT+
FILT+ (Output) - Full-scale reference voltage for ADC.
ADC Common-Mode Voltage (Output) - Filter connections for the ADC internal quiescent refer-
VCMADC
ence voltage.
GND
VA
8
9
Analog Ground (Input) - Analog ground reference.
Analog Power (Input) - Positive power for the internal analog section.
VBIAS
10 Bias Voltage (Output) - Positive reference voltage for the internal DAC.
Mute Control 1 (Output) - Active-low mute output can drive external circuitry to eliminate the
11 clicks and pops associated with any single-rail output. This pin will become a high-impedance out-
put during power-down mode or when an invalid MCLK to LRCK ratio is detected.
MUTEC1
MUTEC2
Mute Control 2 (Output) - Active-low mute output can drive external circuitry to eliminate the
12 clicks and pops associated with any single-rail output. This pin will become a high-impedance out-
put during power-down mode or when an invalid MCLK to LRCK ratio is detected.
10
DS721A6
CIRRUS [ CIRRUS LOGIC ]
