CS42L51
4.5.2
Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).
In hardware mode the CODEC operates in single-speed only. In software mode the CODEC operates in
either quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
Double
Speed
÷ 128
00
01
Single
Speed
÷ 128
÷ 256
÷ 512
LRCK Output
(Equal to Fs)
Half
Speed
10
11
Quarter
Speed
÷ 1
÷ 2
0
1
MCLK
SPEED[1:0]
Double
Speed
÷ 2
00
01
MCLKDIV2
Single
Speed
÷ 2
÷ 4
÷ 8
SCLK Output
Half
Speed
10
11
Quarter
Speed
Figure 18. Master Mode Timing
4.5.3
High-Impedance Digital Output
The serial port may be placed on a clock/data bus that allows multiple masters, without the need for ex-
ternal buffers. The 3ST_SP bit places the internal buffers for the serial port signals in a high-impedance
state, allowing another device to transmit clocks or data without bus contention.
CS42L51
Transmitting Device #2
Transmitting Device #1
SDOUT
3ST_SP
SCLK/LRCK
Receiving Device
Figure 19. Tri-State Serial Port
38
DS679A2
CIRRUS [ CIRRUS LOGIC ]
