CS42L51
4.5
Serial Port Clocking
The CODEC serial audio interface port operates either as a slave or master. It accepts externally generated
clocks in slave mode and will generate synchronous clocks derived from an input master clock (MCLK) in
master mode.
The frequency of the MCLK must be an integer multiple of, and synchronous with, the system sample rate,
Fs. The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked
into or out of the device.
The SPEED and MCLKDIV2 software control bits or the SDOUT/(M/S) and MCLKDIV2 stand-alone control
pins, configure the device to generate the proper clocks in Master Mode and receive the proper clocks in
Slave Mode. The value on the SDOUT pin is latched immediately after powering up in hardware mode.
Software “MIC Power Control & Speed Control (Address 03h)” on page 48, “DAC Control (Address 09h)” on
page 55.
Control:
Hardware
Control:
Pin
Setting
Selection
“SDOUT, M/S” pin
29
47 kΩ Pull-down Slave
47 kΩ Pull-up
Master
“MCLKDIV2” pin 2
LO
HI
No Divide
MCLK is divided by 2 prior to all internal circuitry.
4.5.1
Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the CODEC is automatically determined based
on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will
then require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-
alone control pin.
Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed
mode must be selected using the SPEED[1:0] bits.
Auto-Detect
Disabled
(Software
Mode only)
Enabled
QSM
512, 768, 1024,
1536, 2048, 3072
HSM
SSM
DSM
256, 384, 512, 768, 128, 192, 256, 384, 128, 192, 256, 384
1024, 1536
512, 768
1024, 1536, 2048*,
3072*
512, 768, 1024*,
1536*
256, 384, 512*, 768* 128, 192, 256*, 384*
*MCLKDIV2 must be enabled.
Table 3. MCLK/LRCK Ratios
DS679A2
37
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