CS4228
SWITCHING CHARACTERISTICS - CONTROL PORT
(T
A
= 25°C; VD = VL = +3.3V,
VA = +5V; Inputs: logic 0 = DGND, logic 1 = VL, C
L
= 30 pF)
Parameter
Symbol
(Note 11)
f
scl
t
buf
t
hdst
t
low
t
high
t
sust
(Note 12)
t
hdd
t
sud
t
r
t
f
t
susp
4.7
-
4.7
4.0
4.7
4.0
4.7
0
250
1
300
100
kHz
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
Min
Max
Units
I
2
C
®
Mode
(SDOUT < 47kΩ to ground)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time to SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Notes: 11. Use of the I
2
C bus interface requires a license from Philips. I
2
C is a registered trademark of Philips
Semiconductors.
12. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Stop
SDA
t
buf
Start
Repeated
Start
Stop
t hdst
t high
t
hdst
tf
t susp
SCL
t
t
t sud
t sust
tr
low
hdd
Figure 4. I
2
C Control Port Timing
DS307PP1
9
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