CS4228
SWITCHING CHARACTERISTICS
(Continued)
Parameter
RST Low Time
SCLK Falling Edge to SDOUT Output Valid
LRCK Edge to MSB Valid
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
(Note 8)
(DSCK=0)
t
dpd
t
lrpd
t
ds
t
dh
t
mslr
Symbol
1
Typ
-
-
-
-
-
+10
50
t
sckw
t
sckh
t
sckl
(DSCK=0)
(DSCK=0)
t
lrckd
t
lrcks
TBD
TBD
TBD
TBD
-
-
-
-
-
Max
-
TBD
TBD
TBD
TBD
-
-
-
-
-
-
-
Units
ms
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
Master Mode
SCLK Falling to LRCK Edge
SCLK Duty Cycle
Slave Mode
SCLK Period
SCLK High Time
SCLK Low Time
SCLK rising to LRCK Edge
LRCK Edge to SCLK Rising
Notes: 8. After powering up the CS4228, RST should be held low until the power supplies and clocks are settled.
LRCK
(input)
t lrckd
t
lrcks
t
sckh
t sckl
SCLK*
(output)
t
mslr
LRCK
(output)
SCLK*
(input)
t sckw
SDIN1
SDIN2
SDIN3
t
lrpd
t ds
t dh
MSB
t dpd
MSB-1
SDOUT
SDOUT
*SCLK shown for DSCK = 0.
SCLK inverted for DSCK = 1.
Figure 1. Serial Audio Port Master Mode Timing
Figure 2. Serial Audio Port Slave Mode Timing
DS307PP1
7
CIRRUS [ CIRRUS LOGIC ]
