CS4222
change is adjustable to 4, 16, or 32 LRCK cycles
with the RMP1/0 bits in the DAC control byte
(#2).
they receive between 512 and 1024 consecutive
zeros (or -1 code). Detection and muting is done
independently for left and right channels. A sin-
gle non-zero value will immediately unmute the
DAC output. This feature is enabled on power-
up, and it may be disabled with the MUTC bit in
the DAC Control Byte (#2).
"Soft" volume control may be disabled through
the SOFT bit in the DAC bit Control Byte (#2).
When "soft" volume control is defeated, level
changes step from the current level to the new
level in a single step. The volume change takes
effect on a zero crossing to minimize audible ar-
tifacts. If there is no zero crossing, then the
requested level change will occur after a time-
out period between 512 and 1024 sample periods
(10.7 ms to 21.3 ms at 48 kHz sample rate).
There is a separate zero crossing detector for
each channel. ACCR and ACCL bits in the Con-
verter Status Report Byte (#6) give feedback on
when a volume control change has taken effect
for the right and left channel. This bit goes high
when a new setting is loaded and returns low
when it has taken effect.
Master Clock Generation
The Master Clock, MCLK, is used to operate the
digital filters and the delta-sigma modulator.
MCLK must be either 256x, 384x, or 512x the
desired Input Sample Rate, Fs. Fs is the fre-
quency at which digital audio samples for each
channel are input to the DAC or output from the
ADC and is equal to the LRCK frequency. The
MCLK to LRCK frequency ratio is detected
automatically during the initialization sequence by
counting the number of MCLK transitions during
a single LRCK period. Internal dividers are then
set to generate the proper clocks for the digital
filters, delta-sigma modulators and switched-ca-
pacitor filter. Table 3 illustrates the standard
audio sample rates and the required MCLK fre-
quencies. If MCLK stops for 10µs, the CS4222
will enter a power down state until the clock re-
turns. The control port registers will maintain
their current settings. It is required to have
SCLK and LRCK derived from the master clock.
Soft Mute/Mute on Zero Input Data
Muting can be achieved via hardware or soft-
ware control. Soft mute can be achieved by
lowering the SMUTE pin at which point the out-
put level will ramp down in 0.5 dB steps to a
muted state. Upon returning the SMUTE pin
high, the output will ramp up to the volume con-
trol setting in the Output Attenuator Data Bytes
(#3 & #4). "Soft" mute may be disabled through
the SOFT bit in the DAC Control Byte (#2).
When "soft" mute is defeated, muting occurs on
zero crossings or after a time-out period, similar
to the volume control changes.
Fs (kHz)
MCLK (MHz)
384x
256x
512x
32
44.1
48
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
Table 3. Common Clock Frequencies
Under software control, each output can be inde-
pendently muted via mute control bits, MUTR
and MUTL, in the DAC Control Byte (#2). Soft
mute or zero crossing mute will be implemented
depending on the state of the SOFT bit in the
DAC Control Byte (#2).
Muting on consecutive zero input data is also
provided where all DAC outputs will mute if
12
DS236PP3
CIRRUS [ CIRRUS LOGIC ]
