CS4222
set at the input to the CS4222 will be removed
by the internal high-pass filters. See Figure 3 for
the differential input signal description. The
ADC outputs may be muted (set to zero) by
writing the ADMR and ADML bits, and the
ADC can be independently powered down using
the PDAD bit. ADMR, ADML, and PDAD are
all located in the ADC control byte (#1).
Analog Outputs
Line Level Outputs
The CS4222 contains an on-chip buffer amplifier
producing differential outputs capable of driving
10 kΩ loads. Each output (AOUTL+, AOUTL-,
AOUTR+, AOUTR-) will produce a nominal
2.83 Vpp (1 Vrms) output with a 2.3 volt com-
mon mode for a full scale digital input. This is
equivalent to a 5.66 Vpp (2 Vrms) differential
signal as shown in Figure 3. The recommended
off-chip analog filter is either a 2nd order Butter-
worth or a 3rd order Butterworth, if greater
out-of-band noise filtering is desired. The
CS4222 DAC interpolation filter has been pre-
compensated for an external 2nd order
Butterworth filter with a 3dB corner at Fs, or a
3rd order Butterworth filter with a 3dB corner at
0.75 Fs to provide a flat frequency response and
linear phase over the passband (see Figure 4 for
Fs = 48 kHz). If the recommended filter is not
used, small frequency response magnitude and
phase errors will occur. In addition to providing
out-of-band noise attenuation, the output filters
shown in Figure 4 provide differential to single-
ended conversion.
Input Level Monitoring
The CS4222 includes independent Peak Input
Level Monitoring for each channel. The analog-
to-digital converter continually monitors the peak
digital signal for both channels, prior to the digi-
tal limiter, and records these values in the
LVL2-0 (left channel) and LVR2-0 (right chan-
nel) bits in the Converter Status Report Byte
(#6). These bits indicate whether the input level
is clipping, -1 to -6 dB from full scale in 1 dB
resolution, or below -6 dB from full scale. The
LVL/LVR bits are "sticky" bits and are reset to
zero when read.
High Pass Filter
The operational amplifiers in the input circuitry
driving the CS4222 may generate a small DC
offset into the A/D converter. The CS4222 in-
cludes a high pass filter after the decimator to
remove any DC offset which could result in re-
cording a DC level, possibly yielding "clicks"
when switching between devices in a multichan-
nel system. The characteristics of this first-order
high pass filter are outlined below for Fs equal
to 48 kHz. The filter response scales linearly
with sample rate. The high pass filter may be de-
feated independently for the left and right
channels by writing HPDR and HPDL in the
ADC control byte (#1).
The DACs can be powered down using the
PDDA bit in the DAC control register (#2).
CS4222
(2.3 + 1.4)V
2.3V
AIN+/AOUT+
(2.3 - 1.4)V
(2.3 + 1.4)V
AIN+/AOUT-
2.3V
(2.3 - 1.4)V
Full Scale Input level = (AIN+) - (AIN-)= 5.66 Vpp
Full Scale Output level = (AOUT+) - (AOUT-)= 5.66 Vpp
Frequency Response
-3dB @ 3.7 Hz
-0.1 dB @ 20 Hz
Figure 3. Full Scale Input/Output Voltage
Phase Deviation
Passband Ripple
10 degrees @ 20 Hz
None
Table 2. High Pass Filter Characteristics
10
DS236PP3
CIRRUS [ CIRRUS LOGIC ]
