CS5102A
ANALOG CHARACTERISTICS (continued)
CS5102A -J,K
CS5102A -A,B
CS5102A -S,T
Parameter*
Symbol Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range
Analog Input
-
0 to +70
40 to +85
-55 to +125
°C
Aperture Time
-
-
-
-
30
-
-
-
-
30
-
-
-
30
-
ns
ps
Aperture Jitter
100
100
-
100
-
Input Capacitance
(Note 6)
Unipolar Mode
Bipolar Mode
-
-
-
-
320 425
200 265
-
-
320 425
200 265
-
-
320 425
200 265
pF
pF
Conversion & Throughput
Conversion Time
Acquisition Time
Throughput
(Note 19)
(Note 20)
(Note 21)
t
-
-
-
-
-
40.625
9.375
-
-
-
-
-
-
40.625
9.375
-
-
-
-
-
-
40.625
9.375
-
c
µs
µs
t
a
f
20
20
20
kHz
tp
Power Supplies
Power Supply Current
(Note 22)
Positive Analog
I +
I -
A
I +
D
-
-
-
-
2.4 3.5
-2.4 -3.5
2.5 3.5
-1.5 -2.5
-
-
-
-
2.4 3.5
-2.4 -3.5
2.5 3.5
-1.5 -2.5
-
-
-
-
2.4 3.5
-2.4 -3.5
2.5 3.5
-1.5 -2.5
mA
mA
mA
mA
A
Negative Analog
Positive Digital
Negative Digital
(SLEEP High)
I -
D
Power Consumption
(Notes 11, 22)
(SLEEP High)
P
P
-
-
44
1
65
-
-
-
44
1
65
-
-
-
44
1
65
-
mW
mW
do
(SLEEP Low)
ds
Power Supply Rejection:
(Note 23)
Positive Supplies
Negative Supplies
PSR
PSR
-
-
84
84
-
-
-
-
84
84
-
-
-
-
84
84
-
-
dB
dB
Notes: 19. Conversion time scales directly to the master clock speed. The times shown are for synchronous,
internal loopback (FRN mode). In PDT, RBT, and SSC modes, asynchronous delay between the falling
edge of HOLD and the start of conversion may add to the apparent conversion time. This delay will
not exceed 1 master clock cycle + 140 ns.
20. The CS5102A requires 6 clock cycles of coarse charge, followed by a minimum of 5.625 µs of fine charge.
FRN mode allows 9 clock cycles for fine charge which provides for the minimum 5.625 µs with an 1.6 MHz
clock, however; in PDT, RBT, or SSC modes, at clock frequencies less than 1.6 MHz, fine charge may
be less than 9 clock cycles.
21. Throughput is the sum of the acquisition and conversion times. It will vary in accordance with conditions
affecting acquisition and conversion times, as described above.
22. All outputs unloaded. All inputs at VD+ or DGND. See table below for power dissipation vs. clock frequency.
23. With 300 mV p-p, 1 kHz ripple applied to each supply separately in the bipolar mode. Rejection
improves by 6 dB in the unipolar mode to 90 dB. Figure 23 shows a plot of typical power supply
rejection versus frequency.
Typ. Power (mW) CLKIN (MHz)
34
37
39
41
44
0.8
1.0
1.2
1.4
1.6
6
DS45F2
CIRRUS [ CIRRUS LOGIC ]
