CS5012A, CS5014, CS5016
SWITCHING CHARACTERISTICS
(T
A
= T
MIN
to T
MAX
; VA+, VD+ = 5V
±10%;
VA-, VD- = -5V
±10%;
Inputs: Logic 0 = 0V, Logic 1 = VD+; C
L
= 50 pF, BW = VD+)
Parameter
CS5012A CLKIN Frequency:
Internally Generated:
Externally Supplied:
CS5014/5016 CLKIN Frequency:
Internally Generated:
Externally Supplied:
CLKIN Duty Cycle
Rise Times:
Fall Times:
HOLD Pulse Width
Conversion Time:
CS5012A
CS5014
CS5016
(Note 11)
CAL, INTRLV to CS Low
A0 to CS and RD Low
CS or RD High to A0 Invalid
CS High to CAL, INTRLV Invalid
CS Low to Data Valid
RD Low to Data Valid
A, B, J, K
S, T
A, B, J, K
S, T
Any Digital Input
Any Digital Output
Any Digital Input
Any Digital Output
t
rise
t
fall
t
hpw
t
c
Symbol
f
CLK
-7
-12
f
CLK
-14,
-28,
-14,
-28,
-16
-32
-16
-32
1.75
1
100 kHz
100 kHz
40
-
-
-
-
1/f
CLK
+50
49/f
CLK
+50
57/f
CLK
65/f
CLK
-
4/f
CLK
-20
20
20
50
50
-
-
-
-
-
-
-
-
2/f
CLK
-50
2/f
CLK
-100
-
-
-
-
-
-
20
-
20
-
-
-
-
40
-
10
10
30
30
90
115
90
90
90
90
2/f
CLK
2/f
CLK
2/f
CLK
2/f
CLK
-
-
4
2
60
1.0
-
1.0
-
t
c
53/f
CLK
+235
61/f
CLK
+235
69/f
CLK
+235
100
-
-
-
-
-
120
150
120
150
110
140
-
-
-
-
MHz
MHz
MHz
MHz
%
µs
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.75
100 kHz
100 kHz
-
-
-
-
6.4
4.0
MHz
MHz
MHz
Min
Typ
Max
Units
Data Delay Time
EOC Pulse Width
Set Up Times:
Hold Times:
Access Times:
t
dd
t
epw
t
cs
t
as
t
ah
t
ch
t
ca
t
ra
t
fd
t
pwl
t
pwh
t
ss
t
sh
Output Float Delay:
K, B
CS or RD High to Output Hi-Z
T
Serial Clock
Set Up Times:
Hold Times:
Pulse Width Low
Pulse Width High
SDATA to SCLK Rising
SCLK Rising to SDATA
Notes: 11. EOC remains low 4 CLKIN cycles if CS and RD are held low. Otherwise, it returns high
within 4 CLKIN cycles from the start of a data read operation or a conversion cycle.
2-14
DS14F6
CIRRUS [ CIRRUS LOGIC ]
