CS5012A, CS5014, CS5016
AIN
VREF
AGND
S1
C/X
C
C/2
C/4
C/8
C/X
CS5012A X = 2048
CS5014 X = 8192
CS5016 X = 32768
CS5012A:
CS5014:
CS5016:
Bit 11
Bit 10
Bit 12
Bit 14
Bit 9
Bit 11
Bit 13
Bit 8
Bit 10
Bit 12
Bit 0 Dummy
LSB
Bit 13
Bit 15
MSB
C
= C + C/2 + C/4 + ... + C/X
tot
Figure 1. Charge Redistribution DAC
THEORY OF OPERATION
algorithm. Instead of the traditional resistor net-
work, the DAC is an array of binary-weighted
capacitors. All capacitors in the array share a
common node at the comparator’s input. Their
other terminals are capable of being connected to
AIN, AGND, or VREF (Figure 1). When the de-
vice is not calibrating or converting, all capacitors
The CS5012A/14/16 family utilize a successive
approximation conversion technique. The analog
input is successively compared to the output of a
D/A converter controlled by the conversion algo-
rithm. Successive approximation begins by
comparing the analog input to the DAC output
which is set to half-scale (MSB on, all other bits
off). If the input is found to be below half-scale,
the MSB is reset to zero and the input is com-
pared to one-quarter scale (next MSB on, all
others off). If the input were above half-scale, the
MSB would remain high and the next compari-
son would be at three-quarters of full scale. This
procedure continues until all bits have been exer-
cised.
are tied to AIN forming C . Switch S1 is closed
tot
and the charge on the array, Q , tracks the input
in
signal V (Figure 2a).
in
When the conversion command is issued, switch
S1 opens as shown in Figure 2b. This traps
charge Q on the comparator side of the capaci-
in
tor array and creates a floating node at the
comparator’s input. The conversion algorithm op-
erates on this fixed charge, and the signal at the
analog input pin is ignored. In effect, the entire
DAC capacitor array serves as analog memory
A unique charge redistribution architecture is
used to implement the successive approximation
.
D C
tot
S1
S1
VREF
AGND
Q
in
Q
in
+
AIN
V
+
fn
-
To MCU
V
C
in
tot
To MCU
-
(1-D) C
tot
V
in
D =
for V = 0V
fn
-Q = V
C
in in tot
VREF
Figure 2a. Tracking Mode
Figure 2b. Convert Mode
DS14F6
2-17
CIRRUS [ CIRRUS LOGIC ]
