CS7054
Application Information: continued
Overvoltage Shutdown
On Time = C
FLT
´
2.4V - 0.6V
I
AVG
The IC will disable the output during an overvoltage
event. This is a real time fault event and does not set the
internal latch and therefore is independent of the oscillator
timing (i.e. asynchronous). There is no undervoltage lock-
out. The device will shutdown gracefully once it runs out
of headroom.
where:
I
AVG
= (295.5µA
´
DC) - [4.5µA
´
(1 - DC)]
I
AVG
= (300µA
´
DC) - 4.5µA
DC = PWM Duty Cycle
Sleep State
This device will enter into a low current mode (<275µA)
when CTL lead is brought to less than 0.5V. All functions
are disabled in this mode, except for the regulator.
Reverse Battery
The CS7054 will not survive a reverse battery condition.
Therefore, a series diode is required between the battery
and the V
CC
lead.
Load Dump
V
CC
is internally clamped to 30V. It is recommended that a
51�½ resistor, (R
S
) is placed in series with V
CC
to limit the
current flow into the IC in the event of a 40V peak tran-
sient condition.
Inhibit
When the inhibit voltage is greater than 2.5V the internal
latch is set and the external MOSFET will be turned off for
the remainder of the oscillator cycle. The latch is then reset
at the start of the next cycle.
5
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
