CS7054
Application Information: continued
in the supply voltage. The duty cycle is varied based upon
the input voltage and supply voltage by the following
equation:
2.8
´
V
CTL
V
CC
tial voltage across these two leads is amplified internally
and compared to the voltage at the I
ADJ
lead. The gain, A
V
,
is set internally and externally by the following equation:
V
I(ADJ)
I
SENSE+
- I
SENSE-
Duty Cycle = 100%
´
A
V
=
=
37000
1000 + R
CS
An internal DC voltage equal to:
V
DC
= (1.683
´
V
CTL
) + (V
VALLEY
)
is compared to the oscillator voltage to produce the com-
pensated duty cycle. The transfer is set up so that at V
CC
=
14V the duty will equal V
CTL
divided by V
REG
. For exam-
ple at V
CC
= 14V, V
REG
= 5V and V
CTL
= 2.5V, the duty
cycle would be 50% at the output. This would place a 7V
average voltage across the load. If V
CC
then drops to 10V,
the IC would change the duty cycle to 70% and hence keep
the average load voltage at 7V.
The current limit (I
LIM
) is set by the external current sense
resistor (R
SENSE
) placed across the I
SENSE+
and I
SENSE-
ter-
minals and the voltage at the I
ADJ
lead.
(1000 + R
CS
)
37000
V
I(ADJ)
R
SENSE
I
LIM
=
´
120%
V
CC
= 8V
100%
80%
Duty Cycle( %)
V
CC
= 14V
60%
V
CC
= 16V
40%
The R
CS
resistors and C
CS
components form a differential
low pass filter which filters out high frequency noise gen-
erated by the switching of the external MOSFET and the
associated lead noise. R
CS
also forms an error term in the
gain of the I
LIM
equation because the I
SENSE+
and I
SENSE-
leads are low impedance inputs thereby creating a good
current sensing amplifier. Both leads source 50µA while
the chip is in run mode. R
CS
should be much less than 1000
�½ to minimize error in the I
LIM
equation. I
ADJ
should be
biased between 1V and 4V.
When the current through the external MOSFET exceeds
I
LIM
, an internal latch is set and the output pulls the gate of
the MOSFET low for the remainder of the oscillator cycle
(fault mode). At the start of the next cycle, the latch is reset
and the IC reverts back to run mode until another fault
occurs. If a number of faults occur in a given period of
time, the IC Òtimes outÓ and disables the MOSFET for a
long period of time to let it cool off. This is accomplished
by charging the C
FLT
capacitor each time an over current
condition occurs. If a cycle goes by with no overcurrent
fault occurring, an even smaller amount of charge will be
removed from C
FLT
. If enough faults occur together, even-
tually C
FLT
will charge up to 2.4V and the fault latch will
be set. The fault latch will not be reset until the C
FLT
dis-
charges to 0.6V. This action will continue indefinitely if the
fault persists.
The off time and on time are set by the following:
2.4V - 0.6V
4.5µA
20%
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
CTL Voltage (% of V
REG
)
Figure 1: Voltage Compensation
5V Linear Regulator
There is a 5V, 5mA linear regulator available at the V
REG
lead for external use. This voltage acts as a reference for
many internal and external functions. It has a drop out of
approximately 1.5V at room temperature and does not
require an external capacitor for stability.
Current Sense and Timer
The IC differentially monitors the load current on a cycle
by cycle basis at the I
SENSE+
and I
SENSE-
leads. The differen-
4
Off Time = C
FLT
´
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
