CS5302
4.00
3.50
3.00
2.50
2.00
1.50
If the RC is too fast, during step loads the current
waveform will appear larger than it is (typically for a
few hundred µs) and may trip the current limit at a
level lower than the DC limit.
Adaptive Positioning
7. To set the amount of voltage positioning below the
DAC setting at no load connect a resistor (R
)
V(FB)
1.00
0.50
between the output voltage and the V pin. Choose
FB
R
V(FB)
as;
0.00
0
15
10
5
R
+ NL PositionńV
Bias Current
FB
V(FB)
1/ Apparent Duty Cycle
See Figure 2 for V Bias Current.
8. To set the difference in output voltage between no
load and full load, connect a resistor (R
Figure 13. Normalized Input Filter Capacitor
Ripple Current
FB
)
V(DRP)
between the V
and V pins. R
can be
DESIGN EXAMPLE
DRP
FB
V(DRP)
calculated in two steps. First calculate the difference
between the V and V pin at full load. (The V
Choose the component values for a 5.0 V to 1.6 V, 35 A
converter with lossless current sensing, adaptive positioning
and a 45 A current limit. The adaptive positioning is chosen
DRP
FB
FB
voltage should be the same as the DAC voltage during
closed loop operation.) Then choose the R to
V(DRP)
30 mV above the nominal V
at no load and 40 mV
OUT
source enough current across R ( ) for the desired
V FB
below the no–load position with 35 A out. The peak output
voltage transient is 70 mV max during a 32 A step current.
change in output voltage.
DV
+ I
OUTFL
R CS to V
Gain
DRP
V(DRP)
Current Sensing, Power Stage and
Output Filter Components
where:
R = R or R for one phase;
L
OUTFL
R
S
1. Assume 1.5 mΩ of output filter ESR.
I
is the full load output current.
2.
V
ńV
OUT IN
+ (V * V
)
OUT
R
IN
+ DV
R
ńDV
V(FB)
F C 25 mV
1.6ń5.0
250 k 0.01 mF 25 mV
V(DRP)
OUT
V(DRP)
+ (5.0 * 1.6)
+ 17.4 kW
Calculate Input Filter Capacitor Current Ripple
The procedure below assumes that phases do not overlap
and output inductor ripple current (P–P) is less than the
average output current of one phase.
LńR + .01 mF 17.47 kW + 174 ms
L
Choose R + 2.0 mW
L
9. Calculate Input Current
L + 2.0 mW 174 ms + 348 nH
V
I
OUT
OUT
Efficiency V
3. n/a
I
IN
+
(
)
IN
4.
PwrstgZ
+ R CSA Gainń2.0
L
10. Calculate Duty Cycle (per phase).
+ 2.0 mW 3.15ń2.0 + 3.1 mW
V
OUT
Efficiency V
PwrstgZ ESR
Duty Cycle +
+
+
ConverterZ
(
)
IN
PwrstgZ ) ESR
3.1 mW 1.5 mW
3.1 mW ) 1.5 mW
11. Calculate Apparent Duty Cycle.
^ 1.0 mW
Apparent Duty Cycle + Duty Cycle # of Phases
DVR + 1.0 mW 32 A + 32 mV
12. Calculate Input Filter Capacitor Ripple Current. Use
the chart in Figure NO TAG to calculate the
5. n/a
normalized ripple current (K
) based on the
RMS
Current Limit
reciprocal of Apparent Duty Cycle. Then multiply the
input current by K to obtain the Input Filter
Capacitor Ripple Current.
V
6.
+ R I
L
I(LIM)
OUT(LIM)
CS to I Gain
RMS
LIM
+ 2.0 mW 45 A 6.25
+ 562 mV
Ripple (RMS) + I K
IN
RMS
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