CS5302
APPLICATIONS INFORMATION
FIXED FREQUENCY MULTI–PHASE CONTROL
cycle will terminate earlier providing negative feedback.
The CS5302 provides a Cx input for each phase, but the
CS , V and COMP inputs are common to all phases.
In a multi–phase converter, multiple converters are
connected in parallel and are switched on at different times.
This reduces output current from the individual converters
and increases the apparent ripple frequency. Because several
converters are connected in parallel, output current can ramp
up or down faster than a single converter (with the same
value output inductor) and heat is spread among multiple
components.
REF
FB
Current sharing is accomplished by referencing all phases to
the same V and COMP pins, so that a phase with a larger
FB
current signal will turn off earlier than phases with a smaller
current signal.
Including both current and voltage information in the
feedback signal allows the open loop output impedance of
the power stage to be controlled. When the average output
current is zero, the COMP pin will be only 1/2 of the steady
state ramp height plus the OFFSET above the output
voltage. If the COMP pin is held steady and the inductor
current changes, there must also be a change in the output
voltage. Or, in a closed loop configuration when the output
current changes, the COMP pin must move to keep the same
output voltage. The required change in the output voltage or
COMP pin depends on the scaling of the current feedback
signal and is calculated as
The CS5302 uses a two–phase, fixed frequency,
2
Enhanced V architecture. Each phase is delayed 180° from
the previous phase. Normally GATE(H) transitions high at
the beginning of each oscillator cycle. Inductor current
ramps up until the combination of the current sense signal
and the output ripple trip the PWM comparator and bring
GATE(H) low. Once GATE(H) goes low, it will remain low
until the beginning of the next oscillator cycle. While
2
GATE(H) is high, the enhanced V loop will respond to line
and load transients. Once GATE(H) is low, the loop will not
respond again until the beginning of the next cycle.
DV + R CSA Gain DI
S
2
Therefore, constant frequency Enhanced V will typically
The single–phase power stage output impedance is:
respond within the off–time of the converter.
2
The Enhanced V architecture measures and adjusts
Single Stage Impedance + DVńDI + R CSA Gain.
S
current in each phase. An additional input (Cx) for inductor
The multi–phase power stage output impedance is the
single–phase output impedance divided by the number of
phases. The output impedance of the power stage determines
how the converter will respond during the first few µs of a
transient before the feedback loop has repositioned the
COMP pin.
2
current information has been added to the V loop for each
phase as shown in Figure 7.
SWNODE
C
L
X
R
L
+
CSA
+
+
+
The peak output current of each phase can also be
calculated from;
R
S
OFFSET
V
* V
* V
OFFSET
COMP
R
FB
CSA Gain
CS
REF
I
(per phase) +
PWM
pkout
S
COMP
+
V
OUT
Figure 8 shows the step response of a single phase with the
COMP pin at a fixed level. Before T1 the converter is in
normal steady state operation. The inductor current provides
the PWM ramp through the Current Sense Amplifier. The
PWM cycle ends when the sum of the current signal, voltage
signal and OFFSET exceed the level of the COMP pin. At
T1 the output current increases and the output voltage sags.
The next PWM cycle begins and the cycle continues longer
than previously while the current signal increases enough to
V
FB
+
E.A.
+
DAC
OUT
+
COMP
Figure 7. Enhanced V2 Feedback and Current
Sense Scheme
make up for the lower voltage at the V pin and the cycle
FB
ends at T2. After T2 the output voltage remains lower than
at light load and the current signal level is raised so that the
sum of the current and voltage signal is the same as with the
original load. In a closed loop system the COMP pin would
move higher to restore the output voltage to the original
level.
The inductor current is measured across R , amplified by
S
CSA and summed with the OFFSET and Output Voltage at
the non–inverting input of the PWM comparator. The
inductor current provides the PWM ramp and as inductor
current increases the voltage on the positive pin of the PWM
comparator rises and terminates the PWM cycle. If the
inductor starts the cycle with a higher current, the PWM
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