CS5231-3
Application Information: continued
cally 25°C and allows the IC to recover from a thermal
fault without the need for an external reset signal. The
monitoring circuitry is located near the composite PNP-
NPN output transistor, since this transistor is responsible
for most of the on-chip power dissipation. The combina-
tion of current limit and thermal shutdown will protect the
IC from nearly any fault condition.
Reverse Current Protection
During normal system operation, the auxiliary drive cir-
cuitry will maintain voltage on the V
OUT
pin when V
IN
is
absent. IC reliability and system efficiency are improved
by limiting the amount of reverse current that flows from
V
OUT
to ground and from V
OUT
to V
IN
. Current flows from
V
OUT
to ground through the feedback resistor divider that
sets up the output voltage. This resistor can range in value
from 6kΩ to about 10kΩ, and roughly 500µA will flow in
the typical case. Current flow from V
OUT
to V
IN
will be
limited to leakage current after the IC shuts down. On-chip
RC time constants are such that the output transistor
should be turned off well before V
IN
drops below the V
OUT
voltage.
Calculating Power Dissipation and
Heatsink Requirements
Most linear regulators operate under conditions that result
in high on-chip power dissipation. This results in high
junction temperatures. Since the IC has a thermal shut-
down feature, ensuring the regulator will operate correctly
under normal conditions is an important design considera-
tion. Some heatsinking will usually be required.
Thermal characteristics of an IC depend on four parame-
ters: ambient temperature (T
A
in °C), power dissipation
(P
D
in watts), thermal resistance from the die to the ambi-
ent air (θ
JA
in °C per watt) and junction temperature (T
J
in
°C). The maximum junction temperature is calculated from
the formula below:
T
J(MAX)
= T
A(MAX)
+ (θ
JA
) (P
D(MAX)
)
Maximum ambient temperature and power dissipation are
determined by the design, while
θ
JA
is dependent on the
package manufacturer. The maximum junction tempera-
ture for operation of the CS5231-3 within specification is
150°C. The maximum power dissipation of a linear regula-
tor is given as
P
D(MAX)
= (V
in(MAX)
−
V
OUT(MIN)
) (I
LOAD(MAX)
)
+ (V
IN (MAX)
) (I
Gnd(MAX)
)
where I
Gnd(MAX)
is the IC bias current.
It is possible to change the effective value of
θ
JA
by adding
a heatsink to the design. A heatsink serves in some manner
to raise the effective area of the package, thus improving
the flow of heat from the package into the surrounding air.
Each material in the path of heat flow has its own charac-
teristic thermal resistance, all measured in °C per watt. The
thermal resistances are summed to determine the total
thermal resistance between the die junction and air. There
are three components of interest: junction-to-case thermal
resistance (θ
JC
), case-to-heatsink thermal resistance (θ
CS
)
and heatsink-to-air thermal resistance (θ
SA
). The resulting
equation for junction-to-air thermal resistance is
θ
JA
=
θ
JC
+
θ
CS
+
θ
SA
The value of
θ
JC
for the CS5231-3 is provided in the
Packaging Information section of this data sheet.
θ
CS
can
be considered zero, since heat is conducted out of the
package by the IC leads and the tab of the D
2
PAK package,
and since the IC leads and tab are soldered directly to the
PC board.
Modification of
θ
SA
is the primary means of thermal man-
agement. For surface mount components, this means mod-
ifying the amount of trace metal that connects to the IC.
The thermal capacity of PC board traces is dependent on
how much copper area is used, whether or not the IC is in
direct contact with the metal, whether or not the metal sur-
face is coated with some type of sealant, and whether or
not there is airflow across the PC board. The chart provid-
ed below shows heatsinking capability of a square, single
sided copper PC board trace. The area is given in square
millimeters. It is assumed there is no airflow across the PC
board.
70
Thermal Resistance,
°C/W
60
50
40
30
20
10
0
0
2000
4000
6000
2
)
(mm
PC Board Trace Area
Figure 5: Thermal Resistance Capability of Copper PC Board Metal
Traces
Typical D
2
PAK PC Board Heatsink Design
A typical design of the PC board surface area needed for
the D
2
PAK package is shown below. Calculations were
made assuming V
IN(MAX)
=5.25V, V
OUT(MIN)
= 3.266V,
I
OUT(MAX)
= 500mA, I
Gnd(MAX)
= 5mA and T
A
= 70°C.
P
D
= (5.25V
−
3.266V) (0.5A) + (5.25V) (0.005A) = 1018mW
Maximum temperature rise
∆T
= T
J(MAX)
−
T
A
=
150°C
−
70°C = 80°C.
θ
JA
(worst case) =
∆T/P
D
= 80°C/1.018W = 78.56°C/W
First, we determine the need for heatsinking. If we assume
the maximum
θ
JA
= 50°C/W for the D
2
PAK, the maximum
temperature rise is found to be
∆T
= (P
D
) (θ
JA
) = (1.018W) (50°C/W) = 50.9°C
This is less than the maximum specified operating junction
temperature of 125°C, and no heatsinking is required.
Since the D
2
PAK has a large tab, mounting this part to the
8
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
