CS5231-3
Application Circuit
+5V PCI
C1
33µF
V
OUT
V
IN
CS5231-3
Gnd
AuxDrv
ASIC
V
DD
C3
33µF
*indicates PFET body diode
M1
+3.3V V
AUX
C1
33µF
Application Information
Theory of Operation
The CS5231-3 is a fixed 3.3V linear regulator that contains
an auxiliary drive control feature. When V
IN
is greater than
the typical 4.5V threshold, the IC functions as a linear regu-
lator. It provides up to 500mA of current to a load through
a composite PNP-NPN pass transistor. An output capacitor
greater than 10µF with equivalent series resistance less
than 1Ω is required for compensation. More information is
provided in the Stability Considerations section.
The CS5231-3 provides an auxiliary drive feature that
allows a load to remain powered even if the V
IN
supply for
the IC is absent. An external p-channel FET is the only
additional component required to implement this function
if an auxiliary power supply is available. The PFET gate is
connected to the AuxDrv lead. The PFET drain is connect-
ed to the auxiliary power supply, and the PFET source is
connected to the load. The polarity of this connection is
very important, since the PFET body diode will be connect-
ed between the load and the auxiliary supply. If the PFET
is connected with its drain to the load and its source to the
supply, the body diode will be forward-biased if the auxil-
iary supply is turned off. This will result in the linear regu-
lator providing current to everything on the auxiliary sup-
ply rail.
The AuxDrv lead is internally connected to a 10kΩ resistor
and to a saturating NPN transistor that acts as a switch. If
the V
IN
supply is off, the AuxDrv output will connect the
PFET gate to ground through the 10kΩ resistor, and the
PFET will conduct current to the load.
As the V
IN
supply begins to rise, the AuxDrv lead will also
rise until it reaches a typical voltage of about 650mV. The
NPN transistor connected to the AuxDrv lead will saturate
at this point, and the gate of the PFET will be pulled down
to a typical voltage of about 100mV. The PFET will contin-
ues to conduct current to the load.
The V
IN
supply voltage will continue to rise, but the linear
regulator output is disabled until V
IN
reaches a typical
threshold of 4.5V. During this time, the load continues to
be powered by the auxiliary driver. Once the 4.5V V
IN
threshold is reached, the saturating NPN connected to the
AuxDrv lead turns off. The on-chip 10kΩ pull-up resistor
will pull the PFET gate up to V
IN
, thus turning the PFET
off. The linear regulator turns on at the same time. An
5
external compensation capacitor is required for the linear
regulator to be stable, and this capacitance also serves as a
charge reservoir to minimize any “glitching” that might
result during the supply changeover. Hysteresis is present
in the AuxDrv circuitry, requiring V
IN
to drop by 100mV
(typical) after the linear regulator is providing power to the
load before the AuxDrv circuitry can be re-enabled.
V
IN
V
OUT
V
AUXDRV
I
OUT
= STARTUP 375mA
Figure 1. Initial power-up, V
AUX
not present R
OUT
= 8.8Ω.
V
IN
V
OUT
V
AUXDRV
I
OUT
= 375mA V
AUX
= 3.30V
Figure 2a. Power-up, V
AUX
= 3.30V. Note the “oscillatory performance”
as the linear regulator charges the V
OUT
node. I
OUT
×
R
DS(ON)
≈
130mV
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
